thfu 596b32273b 八倍内插模块的使能改为时钟二分频； ... 八路输出转为四路输出； .m文件计算输入加滤波结果 v04-add valid output port and convert from 8 to 4 Modify the directory structure Modify the directory structure 2th v04-din+IIR_out to compare with verdi v04-add valid output port and convert from 8 to 4 on FPGA		2025-03-11 19:44:53 +08:00
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IIR_Filter.v	八倍内插模块的使能改为时钟二分频；	2025-03-11 19:44:53 +08:00
mult_C.v	八倍内插模块的使能改为时钟二分频；	2025-03-11 19:44:53 +08:00