TailCorr/rtl
thfu 596b32273b 八倍内插模块的使能改为时钟二分频;
八路输出转为四路输出;
.m文件计算输入加滤波结果

v04-add valid output port and convert from 8 to 4

Modify the directory structure

Modify the directory structure 2th

v04-din+IIR_out to compare with verdi

v04-add valid output port and convert from 8 to 4 on FPGA
2025-03-11 19:44:53 +08:00
..
MyIIR 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
OtherFile 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
nco 增加了八倍内插模块; 2025-03-11 19:36:24 +08:00
DW02_mult.v 增加了八倍内插模块; 2025-03-11 19:36:24 +08:00
DW_iir_dc.v IIR滤波器使用IP核; 2025-03-11 19:40:19 +08:00
MeanIntp_8.v 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
TailCorr_top.v 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
diff.v 基于IP核的滤波器,使能二分频 2025-03-11 19:42:44 +08:00
z_dsp.v 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
z_dsp_en_Test.v 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00
z_dsp_wrapper.v 八倍内插模块的使能改为时钟二分频; 2025-03-11 19:44:53 +08:00