70 lines
1.2 KiB
Verilog
70 lines
1.2 KiB
Verilog
module spram_model #(
|
|
parameter width = 32
|
|
,parameter depth = 256
|
|
)(
|
|
clka,
|
|
ena,
|
|
dina,
|
|
addra,
|
|
|
|
clkb,
|
|
enb,
|
|
doutb,
|
|
addrb
|
|
);
|
|
|
|
//=================================================
|
|
function integer clog2(input integer depth);
|
|
begin
|
|
for(clog2=0;depth>0;clog2=clog2+1)
|
|
depth =depth>>1;
|
|
end
|
|
endfunction
|
|
//=================================================
|
|
|
|
localparam aw = clog2(depth-1);
|
|
//=================================================
|
|
input clka;
|
|
input ena;
|
|
input [width-1:0] dina;
|
|
input [aw-1:0] addra;
|
|
|
|
input clkb;
|
|
input enb;
|
|
output [width-1:0] doutb;
|
|
input [aw-1:0] addrb;
|
|
|
|
|
|
//================================================
|
|
wire clka;
|
|
wire ena;
|
|
wire [width-1:0] dina;
|
|
wire [aw-1:0] addra;
|
|
|
|
wire clkb;
|
|
wire enb;
|
|
reg [width-1:0] doutb;
|
|
wire [aw-1:0] addrb;
|
|
|
|
|
|
//================================================
|
|
reg [width-1:0] mem[0:depth-1];
|
|
|
|
always@(posedge clka)begin
|
|
if(!ena)begin
|
|
mem[addra] <=dina;
|
|
end
|
|
end
|
|
|
|
always@(posedge clkb)begin
|
|
if(!enb)begin
|
|
doutb <=mem[addrb];
|
|
end
|
|
else begin
|
|
doutb <=0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|