785 lines
34 KiB
Verilog
785 lines
34 KiB
Verilog
module TB();
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//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : tb_TailCorr_en.v
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// Department : HFNL
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 2025-03-03 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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reg [1 :0] source_mode;
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initial
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begin
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$fsdbDumpfile("TB.fsdb");
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$fsdbDumpvars(0, TB);
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$fsdbDumpMDA();
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// $srandom(417492050);
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source_mode = 2'd3; //1 for rect;2 for random;3 from matlab
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end
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reg rstn;
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reg [31:0] a_re0;
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reg [31:0] a_im0;
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reg [31:0] b_re0;
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reg [31:0] b_im0;
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reg [31:0] ab_re0;
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reg [31:0] ab_im0;
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reg [31:0] abb_re0;
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reg [31:0] abb_im0;
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reg [31:0] ab_pow3_re0;
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reg [31:0] ab_pow3_im0;
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reg [31:0] ab_pow4_re0;
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reg [31:0] ab_pow4_im0;
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reg [31:0] ab_pow5_re0;
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reg [31:0] ab_pow5_im0;
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reg [31:0] ab_pow6_re0;
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reg [31:0] ab_pow6_im0;
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reg [31:0] ab_pow7_re0;
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reg [31:0] ab_pow7_im0;
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reg [31:0] b_pow8_re0;
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reg [31:0] b_pow8_im0;
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reg [31:0] a_re1;
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reg [31:0] a_im1;
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reg [31:0] b_re1;
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reg [31:0] b_im1;
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reg [31:0] ab_re1;
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reg [31:0] ab_im1;
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reg [31:0] abb_re1;
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reg [31:0] abb_im1;
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reg [31:0] ab_pow3_re1;
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reg [31:0] ab_pow3_im1;
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reg [31:0] ab_pow4_re1;
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reg [31:0] ab_pow4_im1;
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reg [31:0] ab_pow5_re1;
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reg [31:0] ab_pow5_im1;
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reg [31:0] ab_pow6_re1;
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reg [31:0] ab_pow6_im1;
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reg [31:0] ab_pow7_re1;
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reg [31:0] ab_pow7_im1;
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reg [31:0] b_pow8_re1;
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reg [31:0] b_pow8_im1;
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reg [31:0] a_re2;
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reg [31:0] a_im2;
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reg [31:0] b_re2;
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reg [31:0] b_im2;
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reg [31:0] ab_re2;
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reg [31:0] ab_im2;
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reg [31:0] abb_re2;
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reg [31:0] abb_im2;
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reg [31:0] ab_pow3_re2;
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reg [31:0] ab_pow3_im2;
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reg [31:0] ab_pow4_re2;
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reg [31:0] ab_pow4_im2;
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reg [31:0] ab_pow5_re2;
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reg [31:0] ab_pow5_im2;
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reg [31:0] ab_pow6_re2;
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reg [31:0] ab_pow6_im2;
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reg [31:0] ab_pow7_re2;
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reg [31:0] ab_pow7_im2;
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reg [31:0] b_pow8_re2;
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reg [31:0] b_pow8_im2;
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reg [31:0] a_re3;
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reg [31:0] a_im3;
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reg [31:0] b_re3;
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reg [31:0] b_im3;
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reg [31:0] ab_re3;
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reg [31:0] ab_im3;
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reg [31:0] abb_re3;
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reg [31:0] abb_im3;
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reg [31:0] ab_pow3_re3;
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reg [31:0] ab_pow3_im3;
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reg [31:0] ab_pow4_re3;
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reg [31:0] ab_pow4_im3;
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reg [31:0] ab_pow5_re3;
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reg [31:0] ab_pow5_im3;
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reg [31:0] ab_pow6_re3;
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reg [31:0] ab_pow6_im3;
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reg [31:0] ab_pow7_re3;
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reg [31:0] ab_pow7_im3;
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reg [31:0] b_pow8_re3;
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reg [31:0] b_pow8_im3;
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reg [31:0] a_re4;
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reg [31:0] a_im4;
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reg [31:0] b_re4;
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reg [31:0] b_im4;
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reg [31:0] ab_re4;
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reg [31:0] ab_im4;
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reg [31:0] abb_re4;
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reg [31:0] abb_im4;
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reg [31:0] ab_pow3_re4;
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reg [31:0] ab_pow3_im4;
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reg [31:0] ab_pow4_re4;
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reg [31:0] ab_pow4_im4;
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reg [31:0] ab_pow5_re4;
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reg [31:0] ab_pow5_im4;
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reg [31:0] ab_pow6_re4;
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reg [31:0] ab_pow6_im4;
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reg [31:0] ab_pow7_re4;
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reg [31:0] ab_pow7_im4;
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reg [31:0] b_pow8_re4;
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reg [31:0] b_pow8_im4;
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reg [31:0] a_re5;
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reg [31:0] a_im5;
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reg [31:0] b_re5;
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reg [31:0] b_im5;
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reg [31:0] ab_re5;
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reg [31:0] ab_im5;
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reg [31:0] abb_re5;
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reg [31:0] abb_im5;
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reg [31:0] ab_pow3_re5;
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reg [31:0] ab_pow3_im5;
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reg [31:0] ab_pow4_re5;
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reg [31:0] ab_pow4_im5;
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reg [31:0] ab_pow5_re5;
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reg [31:0] ab_pow5_im5;
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reg [31:0] ab_pow6_re5;
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reg [31:0] ab_pow6_im5;
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reg [31:0] ab_pow7_re5;
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reg [31:0] ab_pow7_im5;
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reg [31:0] b_pow8_re5;
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reg [31:0] b_pow8_im5;
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reg [15:0] din_rect;
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reg clk;
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initial
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begin
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#0;
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rstn = 1'b0;
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clk = 1'b0;
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a_re0 = 32'd55007237;
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a_re1 = 32'd32690030;
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a_re2 = 32'd429516;
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a_re3 = 32'd0;
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a_re4 = 32'd0;
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a_re5 = 32'd0;
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a_im0 = 32'd0;
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a_im1 = 32'd0;
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a_im2 = 32'd0;
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a_im3 = 32'd0;
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a_im4 = 32'd0;
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a_im5 = 32'd0;
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b_re0 = 32'd2143083068;
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b_re1 = 32'd2145807236;
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b_re2 = 32'd2146812530;
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b_re3 = 32'd2147483648;
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b_re4 = 32'd0;
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b_re5 = 32'd0;
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b_im0 = 32'd0;
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b_im1 = 32'd0;
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b_im2 = 32'd0;
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b_im3 = 32'd0;
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b_im4 = 32'd0;
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b_im5 = 32'd0;
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ab_re0 = 32'd54894517;
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ab_re1 = 32'd32664510;
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ab_re2 = 32'd429381 ;
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ab_re3 = 32'd0;
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ab_re4 = 32'd0;
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ab_re5 = 32'd0;
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ab_im0 = 32'd0;
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ab_im1 = 32'd0;
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ab_im2 = 32'd0;
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ab_im3 = 32'd0;
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ab_im4 = 32'd0;
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ab_im5 = 32'd0;
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abb_re0 = 32'd54782028;
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abb_re1 = 32'd32639011;
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abb_re2 = 32'd429247 ;
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abb_re3 = 32'd0;
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abb_re4 = 32'd0;
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abb_re5 = 32'd0;
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abb_im0 = 32'd0;
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abb_im1 = 32'd0;
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abb_im2 = 32'd0;
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abb_im3 = 32'd0;
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abb_im4 = 32'd0;
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abb_im5 = 32'd0;
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ab_pow3_re0 = 32'd54669770;
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ab_pow3_re1 = 32'd32613532;
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ab_pow3_re2 = 32'd429113 ;
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ab_pow3_re3 = 32'd0;
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ab_pow3_re4 = 32'd0;
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ab_pow3_re5 = 32'd0;
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ab_pow3_im0 = 32'd0;
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ab_pow3_im1 = 32'd0;
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ab_pow3_im2 = 32'd0;
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ab_pow3_im3 = 32'd0;
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ab_pow3_im4 = 32'd0;
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ab_pow3_im5 = 32'd0;
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ab_pow4_re0 = 32'd54557742;
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ab_pow4_re1 = 32'd32588072;
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ab_pow4_re2 = 32'd428979 ;
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ab_pow4_re3 = 32'd0;
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ab_pow4_re4 = 32'd0;
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ab_pow4_re5 = 32'd0;
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ab_pow4_im0 = 32'd0;
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ab_pow4_im1 = 32'd0;
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ab_pow4_im2 = 32'd0;
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ab_pow4_im3 = 32'd0;
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ab_pow4_im4 = 32'd0;
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ab_pow4_im5 = 32'd0;
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ab_pow5_re0 = 32'd54445943;
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ab_pow5_re1 = 32'd32562633;
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ab_pow5_re2 = 32'd428845 ;
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ab_pow5_re3 = 32'd0;
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ab_pow5_re4 = 32'd0;
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ab_pow5_re5 = 32'd0;
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ab_pow5_im0 = 32'd0;
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ab_pow5_im1 = 32'd0;
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ab_pow5_im2 = 32'd0;
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ab_pow5_im3 = 32'd0;
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ab_pow5_im4 = 32'd0;
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ab_pow5_im5 = 32'd0;
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ab_pow6_re0 = 32'd54334374;
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ab_pow6_re1 = 32'd32537213;
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ab_pow6_re2 = 32'd428711 ;
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ab_pow6_re3 = 32'd0;
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ab_pow6_re4 = 32'd0;
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ab_pow6_re5 = 32'd0;
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ab_pow6_im0 = 32'd0;
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ab_pow6_im1 = 32'd0;
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ab_pow6_im2 = 32'd0;
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ab_pow6_im3 = 32'd0;
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ab_pow6_im4 = 32'd0;
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ab_pow6_im5 = 32'd0;
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ab_pow7_re0 = 32'd54223033;
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ab_pow7_re1 = 32'd32511813;
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ab_pow7_re2 = 32'd428577 ;
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ab_pow7_re3 = 32'd0;
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ab_pow7_re4 = 32'd0;
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ab_pow7_re5 = 32'd0;
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ab_pow7_im0 = 32'd0;
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ab_pow7_im1 = 32'd0;
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ab_pow7_im2 = 32'd0;
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ab_pow7_im3 = 32'd0;
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ab_pow7_im4 = 32'd0;
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ab_pow7_im5 = 32'd0;
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b_pow8_re0 = 32'd2112530470;
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b_pow8_re1 = 32'd2134108939;
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b_pow8_re2 = 32'd2142120573;
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b_pow8_re3 = 32'd2147483648;
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b_pow8_re4 = 32'd0;
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b_pow8_re5 = 32'd0;
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b_pow8_im0 = 32'd0;
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b_pow8_im1 = 32'd0;
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b_pow8_im2 = 32'd0;
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b_pow8_im3 = 32'd0;
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b_pow8_im4 = 32'd0;
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b_pow8_im5 = 32'd0;
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din_rect = 16'd0;
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#300;
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rstn = 1'b1;
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end
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always #200 clk = ~clk;
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reg [21:0] cnt;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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cnt <= 22'd0;
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else
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cnt <= cnt + 22'd1;
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initial
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begin
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wait(cnt[16]==1'b1)
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$finish(0);
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end
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wire vldi;
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assign vldi = cnt >= 100 && cnt <=10100;
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reg vldi_r1;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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vldi_r1 <= 1'b0;
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else
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begin
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vldi_r1 <= vldi;
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end
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always@(posedge clk or negedge rstn)
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if(!rstn)
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din_rect <= 22'd0;
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else if(vldi)
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begin
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din_rect <= 16'd30000;
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end
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else
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begin
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din_rect <= 16'd0;
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end
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reg signed [15:0] random_in [0:3];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= 16'd0;
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end
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end
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else if (vldi) begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= $urandom % 30000;
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end
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end
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else begin
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for (int i = 0; i < 4; i = i + 1) begin
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random_in[i] <= 16'd0;
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end
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end
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end
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integer file[3:0];
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reg [15:0] data[3:0];
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integer status[3:0];
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reg [15:0] reg_array[3:0];
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initial begin
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string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};
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for (int i = 0; i < 4; i = i + 1) begin
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file[i] = $fopen(filenames[i], "r");
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if (file[i] == 0) begin
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$display("Failed to open file: %s", filenames[i]);
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$finish;
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end
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end
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end
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reg [0:0] vldi_matlab [3:0];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 4; i = i + 1) begin
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reg_array[i] <= 16'd0;
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vldi_matlab[i] <= 16'd0;
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end
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end else begin
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for (int i = 0; i < 4; i = i + 1) begin
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status[i] = $fscanf(file[i], "%d\n", data[i]);
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vldi_matlab[i] <= 16'd0;
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if (status[i] == 1 ) begin
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reg_array[i] <= data[i];
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vldi_matlab[i] <= 1'b1;
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end
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else begin
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reg_array[i] <= 16'd0;
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vldi_matlab[i] <= 1'b0;
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end
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end
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end
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end
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reg signed [15:0] iir_in[3:0];
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always @(*)
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case(source_mode)
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2'b01 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = din_rect;
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end
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end
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2'b10 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = random_in[i];
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end
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end
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2'b11 : begin
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for (int i = 0; i < 4; i = i + 1) begin
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iir_in[i] = reg_array[i];
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end
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end
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endcase
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wire [1:0] intp_mode;
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assign intp_mode = 2'b10;
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wire [1:0] dac_mode_sel;
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assign dac_mode_sel = 2'b00;
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wire tc_bypass;
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wire vldo;
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wire vldo_ref;
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assign tc_bypass = 1'b0;
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reg en;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 0;
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end
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else begin
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en <= ~en;
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end
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end
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wire signed [15:0] dout_p[7:0];
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wire signed [15:0] dout_ref_p[7:0];
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TailCorr_top inst_TailCorr_top
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(
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.clk (clk ),
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.en (en ),
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.rstn (rstn ),
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.vldi (vldi_matlab[0] ),
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// .dac_mode_sel (dac_mode_sel ),
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// .intp_mode (intp_mode ),
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.din0 (iir_in[0]),
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.din1 (iir_in[1]),
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.din2 (iir_in[2]),
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.din3 (iir_in[3]),
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.a_re0 (a_re0),
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.a_im0 (a_im0),
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.b_re0 (b_re0),
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.b_im0 (b_im0),
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.ab_re0 (ab_re0),
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.ab_im0 (ab_im0),
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.abb_re0 (abb_re0),
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.abb_im0 (abb_im0),
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.ab_pow3_re0 (ab_pow3_re0),
|
|
.ab_pow3_im0 (ab_pow3_im0),
|
|
.ab_pow4_re0 (ab_pow4_re0),
|
|
.ab_pow4_im0 (ab_pow4_im0),
|
|
.ab_pow5_re0 (ab_pow5_re0),
|
|
.ab_pow5_im0 (ab_pow5_im0),
|
|
.ab_pow6_re0 (ab_pow6_re0),
|
|
.ab_pow6_im0 (ab_pow6_im0),
|
|
.ab_pow7_re0 (ab_pow7_re0),
|
|
.ab_pow7_im0 (ab_pow7_im0),
|
|
.b_pow8_re0 (b_pow8_re0),
|
|
.b_pow8_im0 (b_pow8_im0),
|
|
.a_re1 (a_re1),
|
|
.a_im1 (a_im1),
|
|
.b_re1 (b_re1),
|
|
.b_im1 (b_im1),
|
|
.ab_re1 (ab_re1),
|
|
.ab_im1 (ab_im1),
|
|
.abb_re1 (abb_re1),
|
|
.abb_im1 (abb_im1),
|
|
.ab_pow3_re1 (ab_pow3_re1),
|
|
.ab_pow3_im1 (ab_pow3_im1),
|
|
.ab_pow4_re1 (ab_pow4_re1),
|
|
.ab_pow4_im1 (ab_pow4_im1),
|
|
.ab_pow5_re1 (ab_pow5_re1),
|
|
.ab_pow5_im1 (ab_pow5_im1),
|
|
.ab_pow6_re1 (ab_pow6_re1),
|
|
.ab_pow6_im1 (ab_pow6_im1),
|
|
.ab_pow7_re1 (ab_pow7_re1),
|
|
.ab_pow7_im1 (ab_pow7_im1),
|
|
.b_pow8_re1 (b_pow8_re1),
|
|
.b_pow8_im1 (b_pow8_im1),
|
|
.a_re2 (a_re2),
|
|
.a_im2 (a_im2),
|
|
.b_re2 (b_re2),
|
|
.b_im2 (b_im2),
|
|
.ab_re2 (ab_re2),
|
|
.ab_im2 (ab_im2),
|
|
.abb_re2 (abb_re2),
|
|
.abb_im2 (abb_im2),
|
|
.ab_pow3_re2 (ab_pow3_re2),
|
|
.ab_pow3_im2 (ab_pow3_im2),
|
|
.ab_pow4_re2 (ab_pow4_re2),
|
|
.ab_pow4_im2 (ab_pow4_im2),
|
|
.ab_pow5_re2 (ab_pow5_re2),
|
|
.ab_pow5_im2 (ab_pow5_im2),
|
|
.ab_pow6_re2 (ab_pow6_re2),
|
|
.ab_pow6_im2 (ab_pow6_im2),
|
|
.ab_pow7_re2 (ab_pow7_re2),
|
|
.ab_pow7_im2 (ab_pow7_im2),
|
|
.b_pow8_re2 (b_pow8_re2),
|
|
.b_pow8_im2 (b_pow8_im2),
|
|
.a_re3 (a_re3),
|
|
.a_im3 (a_im3),
|
|
.b_re3 (b_re3),
|
|
.b_im3 (b_im3),
|
|
.ab_re3 (ab_re3),
|
|
.ab_im3 (ab_im3),
|
|
.abb_re3 (abb_re3),
|
|
.abb_im3 (abb_im3),
|
|
.ab_pow3_re3 (ab_pow3_re3),
|
|
.ab_pow3_im3 (ab_pow3_im3),
|
|
.ab_pow4_re3 (ab_pow4_re3),
|
|
.ab_pow4_im3 (ab_pow4_im3),
|
|
.ab_pow5_re3 (ab_pow5_re3),
|
|
.ab_pow5_im3 (ab_pow5_im3),
|
|
.ab_pow6_re3 (ab_pow6_re3),
|
|
.ab_pow6_im3 (ab_pow6_im3),
|
|
.ab_pow7_re3 (ab_pow7_re3),
|
|
.ab_pow7_im3 (ab_pow7_im3),
|
|
.b_pow8_re3 (b_pow8_re3),
|
|
.b_pow8_im3 (b_pow8_im3),
|
|
.a_re4 (a_re4),
|
|
.a_im4 (a_im4),
|
|
.b_re4 (b_re4),
|
|
.b_im4 (b_im4),
|
|
.ab_re4 (ab_re4),
|
|
.ab_im4 (ab_im4),
|
|
.abb_re4 (abb_re4),
|
|
.abb_im4 (abb_im4),
|
|
.ab_pow3_re4 (ab_pow3_re4),
|
|
.ab_pow3_im4 (ab_pow3_im4),
|
|
.ab_pow4_re4 (ab_pow4_re4),
|
|
.ab_pow4_im4 (ab_pow4_im4),
|
|
.ab_pow5_re4 (ab_pow5_re4),
|
|
.ab_pow5_im4 (ab_pow5_im4),
|
|
.ab_pow6_re4 (ab_pow6_re4),
|
|
.ab_pow6_im4 (ab_pow6_im4),
|
|
.ab_pow7_re4 (ab_pow7_re4),
|
|
.ab_pow7_im4 (ab_pow7_im4),
|
|
.b_pow8_re4 (b_pow8_re4),
|
|
.b_pow8_im4 (b_pow8_im4),
|
|
.a_re5 (a_re5),
|
|
.a_im5 (a_im5),
|
|
.b_re5 (b_re5),
|
|
.b_im5 (b_im5),
|
|
.ab_re5 (ab_re5),
|
|
.ab_im5 (ab_im5),
|
|
.abb_re5 (abb_re5),
|
|
.abb_im5 (abb_im5),
|
|
.ab_pow3_re5 (ab_pow3_re5),
|
|
.ab_pow3_im5 (ab_pow3_im5),
|
|
.ab_pow4_re5 (ab_pow4_re5),
|
|
.ab_pow4_im5 (ab_pow4_im5),
|
|
.ab_pow5_re5 (ab_pow5_re5),
|
|
.ab_pow5_im5 (ab_pow5_im5),
|
|
.ab_pow6_re5 (ab_pow6_re5),
|
|
.ab_pow6_im5 (ab_pow6_im5),
|
|
.ab_pow7_re5 (ab_pow7_re5),
|
|
.ab_pow7_im5 (ab_pow7_im5),
|
|
.b_pow8_re5 (b_pow8_re5),
|
|
.b_pow8_im5 (b_pow8_im5),
|
|
.dout_p0 (dout_p[0] ),
|
|
.dout_p1 (dout_p[1] ),
|
|
.dout_p2 (dout_p[2] ),
|
|
.dout_p3 (dout_p[3] ),
|
|
.dout_p4 (dout_p[4] ),
|
|
.dout_p5 (dout_p[5] ),
|
|
.dout_p6 (dout_p[6] ),
|
|
.dout_p7 (dout_p[7] ),
|
|
|
|
.vldo (vldo )
|
|
|
|
);
|
|
|
|
TailCorr_top_ref refm_TailCorr_top
|
|
(
|
|
.clk (clk ),
|
|
.en (en ),
|
|
.rstn (rstn ),
|
|
.vldi (vldi_matlab[0] ),
|
|
// .dac_mode_sel (dac_mode_sel ),
|
|
// .intp_mode (intp_mode ),
|
|
.din0 (iir_in[0]),
|
|
.din1 (iir_in[1]),
|
|
.din2 (iir_in[2]),
|
|
.din3 (iir_in[3]),
|
|
.a_re0 (a_re0),
|
|
.a_im0 (a_im0),
|
|
//.b_re0 (b_re0),
|
|
//.b_im0 (b_im0),
|
|
.ab_re0 (ab_re0),
|
|
.ab_im0 (ab_im0),
|
|
.abb_re0 (abb_re0),
|
|
.abb_im0 (abb_im0),
|
|
.ab_pow3_re0 (ab_pow3_re0),
|
|
.ab_pow3_im0 (ab_pow3_im0),
|
|
.ab_pow4_re0 (ab_pow4_re0),
|
|
.ab_pow4_im0 (ab_pow4_im0),
|
|
.ab_pow5_re0 (ab_pow5_re0),
|
|
.ab_pow5_im0 (ab_pow5_im0),
|
|
.ab_pow6_re0 (ab_pow6_re0),
|
|
.ab_pow6_im0 (ab_pow6_im0),
|
|
.ab_pow7_re0 (ab_pow7_re0),
|
|
.ab_pow7_im0 (ab_pow7_im0),
|
|
.b_pow8_re0 (b_pow8_re0),
|
|
.b_pow8_im0 (b_pow8_im0),
|
|
.a_re1 (a_re1),
|
|
.a_im1 (a_im1),
|
|
//.b_re1 (b_re1),
|
|
//.b_im1 (b_im1),
|
|
.ab_re1 (ab_re1),
|
|
.ab_im1 (ab_im1),
|
|
.abb_re1 (abb_re1),
|
|
.abb_im1 (abb_im1),
|
|
.ab_pow3_re1 (ab_pow3_re1),
|
|
.ab_pow3_im1 (ab_pow3_im1),
|
|
.ab_pow4_re1 (ab_pow4_re1),
|
|
.ab_pow4_im1 (ab_pow4_im1),
|
|
.ab_pow5_re1 (ab_pow5_re1),
|
|
.ab_pow5_im1 (ab_pow5_im1),
|
|
.ab_pow6_re1 (ab_pow6_re1),
|
|
.ab_pow6_im1 (ab_pow6_im1),
|
|
.ab_pow7_re1 (ab_pow7_re1),
|
|
.ab_pow7_im1 (ab_pow7_im1),
|
|
.b_pow8_re1 (b_pow8_re1),
|
|
.b_pow8_im1 (b_pow8_im1),
|
|
.a_re2 (a_re2),
|
|
.a_im2 (a_im2),
|
|
//.b_re2 (b_re2),
|
|
//.b_im2 (b_im2),
|
|
.ab_re2 (ab_re2),
|
|
.ab_im2 (ab_im2),
|
|
.abb_re2 (abb_re2),
|
|
.abb_im2 (abb_im2),
|
|
.ab_pow3_re2 (ab_pow3_re2),
|
|
.ab_pow3_im2 (ab_pow3_im2),
|
|
.ab_pow4_re2 (ab_pow4_re2),
|
|
.ab_pow4_im2 (ab_pow4_im2),
|
|
.ab_pow5_re2 (ab_pow5_re2),
|
|
.ab_pow5_im2 (ab_pow5_im2),
|
|
.ab_pow6_re2 (ab_pow6_re2),
|
|
.ab_pow6_im2 (ab_pow6_im2),
|
|
.ab_pow7_re2 (ab_pow7_re2),
|
|
.ab_pow7_im2 (ab_pow7_im2),
|
|
.b_pow8_re2 (b_pow8_re2),
|
|
.b_pow8_im2 (b_pow8_im2),
|
|
.a_re3 (a_re3),
|
|
.a_im3 (a_im3),
|
|
//.b_re3 (b_re3),
|
|
//.b_im3 (b_im3),
|
|
.ab_re3 (ab_re3),
|
|
.ab_im3 (ab_im3),
|
|
.abb_re3 (abb_re3),
|
|
.abb_im3 (abb_im3),
|
|
.ab_pow3_re3 (ab_pow3_re3),
|
|
.ab_pow3_im3 (ab_pow3_im3),
|
|
.ab_pow4_re3 (ab_pow4_re3),
|
|
.ab_pow4_im3 (ab_pow4_im3),
|
|
.ab_pow5_re3 (ab_pow5_re3),
|
|
.ab_pow5_im3 (ab_pow5_im3),
|
|
.ab_pow6_re3 (ab_pow6_re3),
|
|
.ab_pow6_im3 (ab_pow6_im3),
|
|
.ab_pow7_re3 (ab_pow7_re3),
|
|
.ab_pow7_im3 (ab_pow7_im3),
|
|
.b_pow8_re3 (b_pow8_re3),
|
|
.b_pow8_im3 (b_pow8_im3),
|
|
.a_re4 (a_re4),
|
|
.a_im4 (a_im4),
|
|
//.b_re4 (b_re4),
|
|
//.b_im4 (b_im4),
|
|
.ab_re4 (ab_re4),
|
|
.ab_im4 (ab_im4),
|
|
.abb_re4 (abb_re4),
|
|
.abb_im4 (abb_im4),
|
|
.ab_pow3_re4 (ab_pow3_re4),
|
|
.ab_pow3_im4 (ab_pow3_im4),
|
|
.ab_pow4_re4 (ab_pow4_re4),
|
|
.ab_pow4_im4 (ab_pow4_im4),
|
|
.ab_pow5_re4 (ab_pow5_re4),
|
|
.ab_pow5_im4 (ab_pow5_im4),
|
|
.ab_pow6_re4 (ab_pow6_re4),
|
|
.ab_pow6_im4 (ab_pow6_im4),
|
|
.ab_pow7_re4 (ab_pow7_re4),
|
|
.ab_pow7_im4 (ab_pow7_im4),
|
|
.b_pow8_re4 (b_pow8_re4),
|
|
.b_pow8_im4 (b_pow8_im4),
|
|
.a_re5 (a_re5),
|
|
.a_im5 (a_im5),
|
|
//.b_re5 (b_re5),
|
|
//.b_im5 (b_im5),
|
|
.ab_re5 (ab_re5),
|
|
.ab_im5 (ab_im5),
|
|
.abb_re5 (abb_re5),
|
|
.abb_im5 (abb_im5),
|
|
.ab_pow3_re5 (ab_pow3_re5),
|
|
.ab_pow3_im5 (ab_pow3_im5),
|
|
.ab_pow4_re5 (ab_pow4_re5),
|
|
.ab_pow4_im5 (ab_pow4_im5),
|
|
.ab_pow5_re5 (ab_pow5_re5),
|
|
.ab_pow5_im5 (ab_pow5_im5),
|
|
.ab_pow6_re5 (ab_pow6_re5),
|
|
.ab_pow6_im5 (ab_pow6_im5),
|
|
.ab_pow7_re5 (ab_pow7_re5),
|
|
.ab_pow7_im5 (ab_pow7_im5),
|
|
.b_pow8_re5 (b_pow8_re5),
|
|
.b_pow8_im5 (b_pow8_im5),
|
|
.dout_p0 (dout_ref_p[0] ),
|
|
.dout_p1 (dout_ref_p[1] ),
|
|
.dout_p2 (dout_ref_p[2] ),
|
|
.dout_p3 (dout_ref_p[3] ),
|
|
.dout_p4 (dout_ref_p[4] ),
|
|
.dout_p5 (dout_ref_p[5] ),
|
|
.dout_p6 (dout_ref_p[6] ),
|
|
.dout_p7 (dout_ref_p[7] ),
|
|
|
|
.vldo (vldo_ref )
|
|
|
|
);
|
|
|
|
|
|
integer signed In_fid[0:3];
|
|
integer signed dout_fid[0:7];
|
|
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
|
|
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};
|
|
|
|
initial begin
|
|
#0;
|
|
for (int i = 0; i < 4; i = i + 1) begin
|
|
In_fid[i] = $fopen(filenames_in[i]);
|
|
end
|
|
for (int i = 0; i < 8; i = i + 1) begin
|
|
dout_fid[i] = $fopen(filenames_dout[i]);
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (cnt >= 90) begin
|
|
for (int i = 0; i < 4; i = i + 1) begin
|
|
$fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
|
|
end
|
|
// for (int i = 0; i < 8; i = i + 1) begin
|
|
// $fclose(In_fid[i]);
|
|
// end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (vldo && en) begin
|
|
for (int i = 0; i < 8; i = i + 1) begin
|
|
$fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
|
|
end
|
|
// for (int i = 0; i < 8; i = i + 1) begin
|
|
// $fclose(dout_fid[i]);
|
|
// end
|
|
end
|
|
end
|
|
endmodule
|
|
|