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拖尾矫正
15 Commits 4 Branches 0 Tags 22 MiB
Verilog 80.6%
SystemVerilog 13.1%
MATLAB 3.5%
Coq 1.2%
Makefile 1.1%
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unknown 456a9fb479 v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m 2024-11-26 17:57:19 +08:00
edf v01-add round module;intp8 and mult_C using round;Modify the directory structure 2024-11-26 13:34:17 +08:00
rtl v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m 2024-11-26 17:57:19 +08:00
script_m v01-z_dsp delay width debug;add z_dsp.m add diff_plot_py.m 2024-11-26 17:57:19 +08:00
sim v01-add round module;intp8 and mult_C using round;Modify the directory structure 2024-11-26 13:34:17 +08:00
tb v01-enable of clk_div2;8pin to 4pin;valid I/O 2024-11-25 23:05:43 +08:00