140 lines
4.5 KiB
Verilog
140 lines
4.5 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : dacif.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-05-11 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module lsdacif (
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input clk
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,input rstn
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//DAC mode select
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,input [1:0] dac_mode_sel //2'b00:NRZ mode;2'b01:Double data mode;
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//2'b10:Double Double data mode;2'b11:reserve;
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,input [1 :0] intp_mode //2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
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//mixer data input
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,input [15:0] din0
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,input [15:0] din1
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,input [15:0] din2
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,input [15:0] din3
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//data output
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,output [15:0] dout0
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,output [15:0] dout1
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,output [15:0] dout2
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,output [15:0] dout3
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);
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////////////////////////////////////////////////////
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// regs
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////////////////////////////////////////////////////
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reg [15:0] dout0_r ;
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reg [15:0] dout1_r ;
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reg [15:0] dout2_r ;
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reg [15:0] dout3_r ;
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////////////////////////////////////////////////////
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// intp mode select
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////////////////////////////////////////////////////
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/*
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always@(posedge clk) begin
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case(intp_mode)
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2'b00 : begin
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mux_p_0 <= {~din0[15],din0[14:0]};
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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end
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2'b01 : begin
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mux_p_0 <= {~din0[15],din0[14:0]};
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mux_p_1 <= {~din1[15],din1[14:0]};
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mux_p_2 <= 16'h0 ;
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mux_p_3 <= 16'h0 ;
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end
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2'b10 : begin
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mux_p_0 <= {~din0[15],din0[14:0]} ;
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mux_p_1 <= {~din1[15],din1[14:0]} ;
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mux_p_2 <= {~din2[15],din2[14:0]} ;
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mux_p_3 <= {~din3[15],din3[14:0]};
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end
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default : begin
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mux_p_0 <= {~din0[15],din0[14:0]} ;
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mux_p_1 <= {~din1[15],din1[14:0]} ;
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mux_p_2 <= {~din2[15],din2[14:0]} ;
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mux_p_3 <= {~din3[15],din3[14:0]} ;
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end
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endcase
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end
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*/
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////////////////////////////////////////////////////
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// mode select
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////////////////////////////////////////////////////
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always @(posedge clk or negedge rstn) begin
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if(rstn == 1'b0) begin
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dout0_r <= 16'h0;
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dout1_r <= 16'h0;
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dout2_r <= 16'h0;
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dout3_r <= 16'h0;
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end
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else begin
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case(dac_mode_sel)
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2'b00 : begin
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dout0_r <= {~din0[15],din0[14:0]};
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dout1_r <= {~din1[15],din1[14:0]};
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dout2_r <= {~din2[15],din2[14:0]};
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dout3_r <= {~din3[15],din3[14:0]};
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end
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2'b01 : begin
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dout0_r <= {~din0[15],din0[14:0]};
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dout1_r <= {~din0[15],din0[14:0]};
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dout2_r <= {~din1[15],din1[14:0]};
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dout3_r <= {~din1[15],din1[14:0]};
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end
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2'b10 : begin
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dout0_r <= {~din0[15],din0[14:0]};
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dout1_r <= {~din0[15],din0[14:0]};
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dout2_r <= {~din0[15],din0[14:0]};
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dout3_r <= {~din0[15],din0[14:0]};
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end
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default : begin
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dout0_r <= {~din0[15],din0[14:0]};
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dout1_r <= {~din1[15],din1[14:0]};
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dout2_r <= {~din2[15],din2[14:0]};
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dout3_r <= {~din3[15],din3[14:0]};
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end
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endcase
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end
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end
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assign dout0 = dout0_r ;
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assign dout1 = dout1_r ;
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assign dout2 = dout2_r ;
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assign dout3 = dout3_r ;
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endmodule
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