301 lines
14 KiB
Systemverilog
301 lines
14 KiB
Systemverilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : Z_dsp.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.2 2024-10-09 thfu to fit the addition of 8 interpolation
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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(* use_dsp = "yes" *)module z_dsp
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(
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input rstn
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,input clk
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,input en
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//,input tc_bypass
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,input [5:0] vldi_coef
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,input vldi_data
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//,input [1:0] intp_mode
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//,input [1:0] dac_mode_sel
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,input signed [31 :0] a_re [5:0]
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,input signed [31 :0] a_im [5:0]
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,input signed [31 :0] b_re [5:0]
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,input signed [31 :0] b_im [5:0]
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,output signed [15:0] dout0
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,output signed [15:0] dout1
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,output signed [15:0] dout2
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,output signed [15:0] dout3
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,output vldo
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);
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wire signed [15:0] IIR_out;
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wire signed [31:0] ao_re [5:0];
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wire signed [31:0] ao_im [5:0];
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wire signed [31:0] ab_re [5:0];
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wire signed [31:0] ab_im [5:0];
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wire signed [31:0] abb_re [5:0];
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wire signed [31:0] abb_im [5:0];
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wire signed [31:0] ab_pow3_re [5:0];
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wire signed [31:0] ab_pow3_im [5:0];
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wire signed [31:0] ab_pow4_re [5:0];
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wire signed [31:0] ab_pow4_im [5:0];
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wire signed [31:0] ab_pow5_re [5:0];
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wire signed [31:0] ab_pow5_im [5:0];
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wire signed [31:0] ab_pow6_re [5:0];
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wire signed [31:0] ab_pow6_im [5:0];
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wire signed [31:0] ab_pow7_re [5:0];
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wire signed [31:0] ab_pow7_im [5:0];
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wire signed [31:0] b_pow8_re [5:0];
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wire signed [31:0] b_pow8_im [5:0];
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CoefGen inst_CoefGen(
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.clk (clk ),
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.rstn (rstn ),
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.vldi (vldi_coef ),
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.a_re (a_re ),
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.a_im (a_im ),
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.b_re (b_re ),
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.b_im (b_im ),
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.ao_re (ao_re ),
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.ao_im (ao_im ),
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.ab_re (ab_re ),
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.ab_im (ab_im ),
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.abb_re (abb_re ),
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.abb_im (abb_im ),
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.ab_pow3_re (ab_pow3_re ),
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.ab_pow3_im (ab_pow3_im ),
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.ab_pow4_re (ab_pow4_re ),
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.ab_pow4_im (ab_pow4_im ),
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.ab_pow5_re (ab_pow5_re ),
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.ab_pow5_im (ab_pow5_im ),
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.ab_pow6_re (ab_pow6_re ),
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.ab_pow6_im (ab_pow6_im ),
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.ab_pow7_re (ab_pow7_re ),
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.ab_pow7_im (ab_pow7_im ),
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.b_pow8_re (b_pow8_re ),
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.b_pow8_im (b_pow8_im )
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);
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wire signed [15:0] dout_0;
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wire signed [15:0] dout_1;
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wire signed [15:0] dout_2;
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wire signed [15:0] dout_3;
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wire signed [15:0] dout_4;
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wire signed [15:0] dout_5;
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wire signed [15:0] dout_6;
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wire signed [15:0] dout_7;
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reg vldo_TC;
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TailCorr_top inst_TailCorr_top
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(
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.clk (clk ),
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.en (en ),
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.rstn (rstn ),
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.vldi (vldi_data ),
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// .dac_mode_sel (dac_mode_sel ),
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// .intp_mode (intp_mode ),
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.din0 (din0 ),
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.din1 (din1 ),
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.din2 (din2 ),
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.din3 (din3 ),
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.a_re0 (ao_re[0] ),
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.a_im0 (ao_im[0] ),
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.ab_re0 (ab_re[0] ),
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.ab_im0 (ab_im[0] ),
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.abb_re0 (abb_re[0] ),
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.abb_im0 (abb_im[0] ),
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.ab_pow3_re0 (ab_pow3_re[0]),
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.ab_pow3_im0 (ab_pow3_im[0]),
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.ab_pow4_re0 (ab_pow4_re[0]),
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.ab_pow4_im0 (ab_pow4_im[0]),
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.ab_pow5_re0 (ab_pow5_re[0]),
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.ab_pow5_im0 (ab_pow5_im[0]),
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.ab_pow6_re0 (ab_pow6_re[0]),
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.ab_pow6_im0 (ab_pow6_im[0]),
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.ab_pow7_re0 (ab_pow7_re[0]),
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.ab_pow7_im0 (ab_pow7_im[0]),
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.b_pow8_re0 (b_pow8_re[0] ),
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.b_pow8_im0 (b_pow8_im[0] ),
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.a_re1 (ao_re[1] ),
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.a_im1 (ao_im[1] ),
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.ab_re1 (ab_re[1] ),
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.ab_im1 (ab_im[1] ),
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.abb_re1 (abb_re[1] ),
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.abb_im1 (abb_im[1] ),
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.ab_pow3_re1 (ab_pow3_re[1]),
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.ab_pow3_im1 (ab_pow3_im[1]),
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.ab_pow4_re1 (ab_pow4_re[1]),
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.ab_pow4_im1 (ab_pow4_im[1]),
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.ab_pow5_re1 (ab_pow5_re[1]),
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.ab_pow5_im1 (ab_pow5_im[1]),
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.ab_pow6_re1 (ab_pow6_re[1]),
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.ab_pow6_im1 (ab_pow6_im[1]),
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.ab_pow7_re1 (ab_pow7_re[1]),
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.ab_pow7_im1 (ab_pow7_im[1]),
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.b_pow8_re1 (b_pow8_re[1] ),
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.b_pow8_im1 (b_pow8_im[1] ),
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.a_re2 (ao_re[2] ),
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.a_im2 (ao_im[2] ),
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.ab_re2 (ab_re[2] ),
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.ab_im2 (ab_im[2] ),
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.abb_re2 (abb_re[2] ),
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.abb_im2 (abb_im[2] ),
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.ab_pow3_re2 (ab_pow3_re[2]),
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.ab_pow3_im2 (ab_pow3_im[2]),
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.ab_pow4_re2 (ab_pow4_re[2]),
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.ab_pow4_im2 (ab_pow4_im[2]),
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.ab_pow5_re2 (ab_pow5_re[2]),
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.ab_pow5_im2 (ab_pow5_im[2]),
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.ab_pow6_re2 (ab_pow6_re[2]),
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.ab_pow6_im2 (ab_pow6_im[2]),
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.ab_pow7_re2 (ab_pow7_re[2]),
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.ab_pow7_im2 (ab_pow7_im[2]),
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.b_pow8_re2 (b_pow8_re[2] ),
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.b_pow8_im2 (b_pow8_im[2] ),
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.a_re3 (ao_re[3] ),
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.a_im3 (ao_im[3] ),
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.ab_re3 (ab_re[3] ),
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.ab_im3 (ab_im[3] ),
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.abb_re3 (abb_re[3] ),
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.abb_im3 (abb_im[3] ),
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.ab_pow3_re3 (ab_pow3_re[3]),
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.ab_pow3_im3 (ab_pow3_im[3]),
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.ab_pow4_re3 (ab_pow4_re[3]),
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.ab_pow4_im3 (ab_pow4_im[3]),
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.ab_pow5_re3 (ab_pow5_re[3]),
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.ab_pow5_im3 (ab_pow5_im[3]),
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.ab_pow6_re3 (ab_pow6_re[3]),
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.ab_pow6_im3 (ab_pow6_im[3]),
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.ab_pow7_re3 (ab_pow7_re[3]),
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.ab_pow7_im3 (ab_pow7_im[3]),
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.b_pow8_re3 (b_pow8_re[3] ),
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.b_pow8_im3 (b_pow8_im[3] ),
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.a_re4 (ao_re[4] ),
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.a_im4 (ao_im[4] ),
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.ab_re4 (ab_re[4] ),
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.ab_im4 (ab_im[4] ),
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.abb_re4 (abb_re[4] ),
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.abb_im4 (abb_im[4] ),
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.ab_pow3_re4 (ab_pow3_re[4]),
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.ab_pow3_im4 (ab_pow3_im[4]),
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.ab_pow4_re4 (ab_pow4_re[4]),
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.ab_pow4_im4 (ab_pow4_im[4]),
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.ab_pow5_re4 (ab_pow5_re[4]),
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.ab_pow5_im4 (ab_pow5_im[4]),
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.ab_pow6_re4 (ab_pow6_re[4]),
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.ab_pow6_im4 (ab_pow6_im[4]),
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.ab_pow7_re4 (ab_pow7_re[4]),
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.ab_pow7_im4 (ab_pow7_im[4]),
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.b_pow8_re4 (b_pow8_re[4] ),
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.b_pow8_im4 (b_pow8_im[4] ),
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.a_re5 (ao_re[5] ),
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.a_im5 (ao_im[5] ),
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.ab_re5 (ab_re[5] ),
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.ab_im5 (ab_im[5] ),
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.abb_re5 (abb_re[5] ),
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.abb_im5 (abb_im[5] ),
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.ab_pow3_re5 (ab_pow3_re[5]),
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.ab_pow3_im5 (ab_pow3_im[5]),
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.ab_pow4_re5 (ab_pow4_re[5]),
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.ab_pow4_im5 (ab_pow4_im[5]),
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.ab_pow5_re5 (ab_pow5_re[5]),
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.ab_pow5_im5 (ab_pow5_im[5]),
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.ab_pow6_re5 (ab_pow6_re[5]),
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.ab_pow6_im5 (ab_pow6_im[5]),
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.ab_pow7_re5 (ab_pow7_re[5]),
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.ab_pow7_im5 (ab_pow7_im[5]),
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.b_pow8_re5 (b_pow8_re[5] ),
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.b_pow8_im5 (b_pow8_im[5] ),
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.dout_p0 (dout_0 ),
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.dout_p1 (dout_1 ),
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.dout_p2 (dout_2 ),
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.dout_p3 (dout_3 ),
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.dout_p4 (dout_4 ),
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.dout_p5 (dout_5 ),
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.dout_p6 (dout_6 ),
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.dout_p7 (dout_7 ),
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.vldo (vldo_TC )
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);
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/*
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parameter Delay = 2;
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reg [Delay:0] vldo_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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vldo_r <= 2'b0;
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end
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else
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begin
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vldo_r <= {vldo_r[Delay:0], vldo_TC};//Delay with 9 clk
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end
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*/
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assign vldo = vldo_TC;
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reg signed [15:0] doutf_0;
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reg signed [15:0] doutf_1;
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reg signed [15:0] doutf_2;
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reg signed [15:0] doutf_3;
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always@(posedge clk or negedge rstn)
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if(!rstn) begin
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doutf_0 <= 0;
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doutf_1 <= 0;
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doutf_2 <= 0;
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doutf_3 <= 0;
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end
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else if(!en) begin
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doutf_0 <= dout_0;
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doutf_1 <= dout_1;
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doutf_2 <= dout_2;
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doutf_3 <= dout_3;
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end
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else begin
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doutf_0 <= dout_4;
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doutf_1 <= dout_5;
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doutf_2 <= dout_6;
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doutf_3 <= dout_7;
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end
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assign dout0 = doutf_0;
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assign dout1 = doutf_1;
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assign dout2 = doutf_2;
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assign dout3 = doutf_3;
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endmodule
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