151 lines
4.2 KiB
Verilog
151 lines
4.2 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : TailCorr_top.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-05-15 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module diff_p
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(
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input rstn
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,input clk
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,input en
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,input vldi
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,output vldo
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,output signed [15:0] dout_p0
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,output signed [15:0] dout_p1
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,output signed [15:0] dout_p2
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,output signed [15:0] dout_p3
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,output signed [15:0] dout_p4
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,output signed [15:0] dout_p5
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,output signed [15:0] dout_p6
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,output signed [15:0] dout_p7
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,output signed [15:0] diff_p0
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,output signed [15:0] diff_p1
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,output signed [15:0] diff_p2
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,output signed [15:0] diff_p3
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,output signed [15:0] diff_p4
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,output signed [15:0] diff_p5
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,output signed [15:0] diff_p6
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,output signed [15:0] diff_p7
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);
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wire [15:0] din_wire [0:3];
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assign din_wire[0] = din0;
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assign din_wire[1] = din1;
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assign din_wire[2] = din2;
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assign din_wire[3] = din3;
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wire [3:0] vldo_temp;
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wire signed [15:0] dinp_r0 [7:0];
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin: s2p_inst
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s2p_2 inst_s2p_2 (
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.clk (clk),
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.rst_n (rstn),
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.din (din_wire[i]),
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.en (vldi),
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.dout0 (dinp_r0[i]),
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.dout1 (dinp_r0[i+4]),
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.vldo (vldo_temp[i])
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);
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end
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endgenerate
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assign vldo = vldo_temp[0];
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reg signed [15:0] dinp_r1 [0:7];
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integer j;
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (j = 0; j < 8; j = j + 1) begin
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dinp_r1[j] <= 'h0;
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end
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end
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else if (en) begin
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for (j = 0; j < 8; j = j + 1) begin
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dinp_r1[j] <= dinp_r0[j];
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end
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end
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end
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wire signed [15:0] diffp_r0 [0:7];
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generate
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for (i = 0; i < 8; i = i + 1) begin: diff_assign
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if (i == 0)
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assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
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else
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assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
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end
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endgenerate
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assign dout_p0 = dinp_r1[0];
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assign dout_p1 = dinp_r1[1];
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assign dout_p2 = dinp_r1[2];
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assign dout_p3 = dinp_r1[3];
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assign dout_p4 = dinp_r1[4];
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assign dout_p5 = dinp_r1[5];
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assign dout_p6 = dinp_r1[6];
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assign dout_p7 = dinp_r1[7];
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reg signed [15:0] diffp_r1 [0:7];
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always @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (j = 0; j < 8; j = j + 1) begin
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diffp_r1[j] <= 0;
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end
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end
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else if (en) begin
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for (j = 0; j < 8; j = j + 1) begin
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diffp_r1[j] <= diffp_r0[j];
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end
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end
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end
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assign diff_p0 = diffp_r1[0];
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assign diff_p1 = diffp_r1[1];
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assign diff_p2 = diffp_r1[2];
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assign diff_p3 = diffp_r1[3];
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assign diff_p4 = diffp_r1[4];
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assign diff_p5 = diffp_r1[5];
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assign diff_p6 = diffp_r1[6];
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assign diff_p7 = diffp_r1[7];
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endmodule
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