418 lines
16 KiB
Verilog
Executable File
418 lines
16 KiB
Verilog
Executable File
////////////////////////////////////////////////////////////////////////////////
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//
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// This confidential and proprietary software may be used only
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// as authorized by a licensing agreement from Synopsys Inc.
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// In the event of publication, the following notice is applicable:
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//
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// (C) COPYRIGHT 1995 - 2018 SYNOPSYS INC.
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// ALL RIGHTS RESERVED
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//
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// The entire notice above must be reproduced on all authorized
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// copies.
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//
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// AUTHOR: KB May 20, 1995
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//
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// VERSION: Verilog Simulation Model for DW_iir_dc
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//
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// DesignWare_version: 10b10551
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// DesignWare_release: O-2018.06-DWBB_201806.1
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//
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////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------------
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//
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// ABSTRACT: Verilog simulation model for IIR filter with dynamic coefficients
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//
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// MODIFIED:
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// Doug Lee 06/02/2008
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// Fix for STAR#9000245949
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// data_out and saturation results were wrong
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// compared to synthetic and VHDL simulation
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// models in a specific negative number
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// boundary case. Re-wrote rounding/saturation
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// function to resemble VHDL simulation model
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// approach.
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//
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// Zhijun (Jerry) Huang 02/12/2004
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// Changed interface names
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// Added parameter legality check
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// Added asynchronous reset signal rst_n
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// Added optional output register controlled by parameter out_reg
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// Added X-processing
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// Fixed verilog analysis warning about zero multiconcat multiplier
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// Fixed verilog analysis error about negative array index
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// Fixed logic errors with saturation and negative/positive handling
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// Fixed logic errors with feedback_data when feedback_width > data_out_width
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//
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//-----------------------------------------------------------------------------------
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module DW_iir_dc(clk,rst_n,init_n,enable,
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A1_coef,A2_coef,B0_coef,B1_coef,B2_coef,
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data_in,data_out,saturation);
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parameter integer data_in_width = 8;
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parameter integer data_out_width = 16;
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parameter integer frac_data_out_width = 4;
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parameter integer feedback_width = 12;
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parameter integer max_coef_width = 8;
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parameter integer frac_coef_width = 4;
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parameter integer saturation_mode = 0;
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parameter integer out_reg = 1;
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input clk,rst_n,init_n,enable;
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input [max_coef_width-1:0] A1_coef,A2_coef,B0_coef,B1_coef,B2_coef;
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input [data_in_width-1:0] data_in;
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output [data_out_width-1:0] data_out;
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output saturation;
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parameter integer psum_width = (feedback_width-frac_data_out_width > data_in_width)?
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feedback_width+max_coef_width+3
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: data_in_width+frac_data_out_width+max_coef_width+3;
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// synopsys translate_off
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function [feedback_width+data_out_width:0] rnd_sat;
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input [psum_width-1:0] psum0;
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reg signed [psum_width:0] psum0_shiftedby1;
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reg signed [data_out_width-1:0] data_out_noreg;
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reg signed [feedback_width-1:0] feedback_data;
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reg signed [frac_coef_width:0] round_limit;
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reg signed [frac_coef_width-1:0] psum0_frac_part;
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reg signed [data_out_width-1:0] max_pos_output;
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reg signed [data_out_width-1:0] max_neg_output;
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reg signed [feedback_width-1:0] max_pos_feedback;
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reg signed [feedback_width-1:0] max_neg_feedback;
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reg signed [data_out_width-1:0] output_inc_data;
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reg signed [feedback_width-1:0] feedback_inc_data;
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reg output_to_big;
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reg feedback_to_big;
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reg saturation_internal;
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integer i, j, k, l;
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begin
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for (i=0; i<data_out_width; i=i+1) begin
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if (i == data_out_width-1)
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max_pos_output[i] = 0;
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else
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max_pos_output[i] = 1;
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end
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for (j=0; j<data_out_width; j=j+1) begin
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if (j == data_out_width-1)
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max_neg_output[j] = 1;
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else if (j == 0)
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if (saturation_mode == 0)
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max_neg_output[j] = 0;
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else
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max_neg_output[j] = 1;
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else
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max_neg_output[j] = 0;
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end
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for (k=0; k<feedback_width; k=k+1) begin
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if (k == feedback_width-1)
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max_pos_feedback[k] = 0;
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else
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max_pos_feedback[k] = 1;
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end
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for (l=0; l<feedback_width; l=l+1) begin
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if (l == feedback_width-1)
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max_neg_feedback[l] = 1;
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else if (l == 0)
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if (saturation_mode == 0)
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max_neg_feedback[l] = 0;
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else
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max_neg_feedback[l] = 1;
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else
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max_neg_feedback[l] = 0;
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end
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// round_limit = -2^(frac_coef_width-1)
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for (i=0; i<=frac_coef_width; i=i+1) begin
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if (i == frac_coef_width)
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round_limit[i] = 1;
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else if (i == frac_coef_width-1)
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round_limit[i] = 1;
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else
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round_limit[i] = 0;
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end
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if (frac_coef_width > 0) begin
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psum0_shiftedby1 = psum0 << 1;
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// Break out the frac_coef portion of psum0
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for (i=0; i<frac_coef_width; i=i+1) begin
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psum0_frac_part[i] = psum0[i];
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end
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_output, 1'b1})) begin
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data_out_noreg = max_pos_output;
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output_to_big = 1;
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end else begin
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_output)) begin
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data_out_noreg = max_neg_output;
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output_to_big = 1;
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end else begin
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if (psum0_shiftedby1[frac_coef_width] &&
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(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
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output_inc_data = psum0[data_out_width+frac_coef_width-1:frac_coef_width] + 1;
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data_out_noreg = output_inc_data;
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output_to_big = 0;
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end else begin
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data_out_noreg = psum0[data_out_width+frac_coef_width-1:frac_coef_width];
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output_to_big = 0;
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end
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end
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end
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width]) >= $signed({max_pos_feedback, 1'b1})) begin
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feedback_data = max_pos_feedback;
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feedback_to_big = 1;
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end else begin
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if ($signed(psum0_shiftedby1[psum_width:frac_coef_width+1]) < $signed(max_neg_feedback)) begin
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feedback_data = max_neg_feedback;
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feedback_to_big = 1;
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end else begin
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if (psum0_shiftedby1[frac_coef_width] &&
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(!psum0_shiftedby1[psum_width] || (($signed(psum0_frac_part)) > $signed(round_limit)))) begin
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feedback_inc_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width] + 1;
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feedback_data = feedback_inc_data;
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feedback_to_big = 0;
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end else begin
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feedback_data = psum0[feedback_width+frac_coef_width-1:frac_coef_width];
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feedback_to_big = 0;
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end
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end
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end
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end else begin
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if ($signed(psum0) > $signed(max_pos_output)) begin
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data_out_noreg = max_pos_output;
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output_to_big = 1;
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end else begin
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if ($signed(psum0) < $signed(max_neg_output)) begin
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data_out_noreg = max_neg_output;
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output_to_big = 1;
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end else begin
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data_out_noreg = psum0[data_out_width-1:0];
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output_to_big = 0;
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end
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end
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if ($signed(psum0) > $signed(max_pos_feedback)) begin
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feedback_data = max_pos_feedback;
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feedback_to_big = 1;
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end else begin
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if ($signed(psum0) < $signed(max_neg_feedback)) begin
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feedback_data = max_neg_feedback;
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feedback_to_big = 1;
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end else begin
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feedback_data = psum0[feedback_width-1:0];
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feedback_to_big = 0;
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end
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end
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end
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saturation_internal = output_to_big || feedback_to_big;
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rnd_sat = {saturation_internal, feedback_data, data_out_noreg};
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end
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endfunction
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wire [data_in_width-1:0] gated_data_in;
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wire [feedback_width-1:0] feedback_data;
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wire [max_coef_width-1:0] A1_coef_wire,A2_coef_wire,
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B0_coef_wire,B1_coef_wire,B2_coef_wire;
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wire [data_in_width+max_coef_width-1:0] B0_product,B1_product,B2_product;
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wire [feedback_width+max_coef_width-1:0] A1_product,A2_product;
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wire [psum_width-3:0] psum2;
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reg [psum_width-3:0] psum2_saved;
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wire [psum_width-1:0] psum1,psum0;
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reg [psum_width-1:0] psum1_saved;
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wire [data_out_width-1:0] data_out_internal;
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wire saturation_internal;
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reg [data_out_width-1:0] data_out_reg;
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reg saturation_reg;
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assign A1_coef_wire = A1_coef;
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assign A2_coef_wire = A2_coef;
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assign B0_coef_wire = B0_coef;
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assign B1_coef_wire = B1_coef;
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assign B2_coef_wire = B2_coef;
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assign gated_data_in = (init_n === 1'b0) ? {data_in_width{1'b0}} : data_in;
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DW02_mult #(data_in_width,max_coef_width) B0_mult(gated_data_in,B0_coef_wire,1'b1,B0_product);
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DW02_mult #(data_in_width,max_coef_width) B1_mult(gated_data_in,B1_coef_wire,1'b1,B1_product);
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DW02_mult #(data_in_width,max_coef_width) B2_mult(gated_data_in,B2_coef_wire,1'b1,B2_product);
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DW02_mult #(feedback_width,max_coef_width) A1_mult(feedback_data,A1_coef_wire,1'b1,A1_product);
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DW02_mult #(feedback_width,max_coef_width) A2_mult(feedback_data,A2_coef_wire,1'b1,A2_product);
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assign psum2 = ({{psum_width{B2_product[data_in_width+max_coef_width-1]}},
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B2_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
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+ {{psum_width{A2_product[feedback_width+max_coef_width-1]}},
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A2_product[feedback_width+max_coef_width-2:0]};
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assign psum1 = ({{psum_width{B1_product[data_in_width+max_coef_width-1]}},
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B1_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
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+ {{psum_width{A1_product[feedback_width+max_coef_width-1]}},
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A1_product[feedback_width+max_coef_width-2:0]}
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+ {{3{psum2_saved[psum_width-3]}},
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psum2_saved[psum_width-4:0]};
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assign psum0 = ({{psum_width{B0_product[data_in_width+max_coef_width-1]}},
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B0_product[data_in_width+max_coef_width-2:0]} << frac_data_out_width)
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+ psum1_saved;
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assign {saturation_internal,feedback_data,data_out_internal} = rnd_sat(psum0);
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always @ (posedge clk or negedge rst_n)
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if (rst_n === 1'b0) begin
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psum2_saved <= {psum_width-2{1'b0}};
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psum1_saved <= {psum_width{1'b0}};
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data_out_reg <= {data_out_width{1'b0}};
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saturation_reg <= 1'b0;
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end
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else if (rst_n === 1'b1) begin
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if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) ||
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(^(A2_coef ^ A2_coef) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) || (^(B2_coef ^ B2_coef) !== 1'b0) ||
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(^(data_in ^ data_in) !== 1'b0) || (^(psum1_saved ^ psum1_saved) !== 1'b0))
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psum2_saved <= {psum_width-2{1'bx}};
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else if (init_n === 1'b0)
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psum2_saved <= {psum_width-2{1'b0}};
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else if (enable === 1'b1)
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psum2_saved <= psum2;
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else
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psum2_saved <= psum2_saved;
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if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) ||
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(^(A1_coef ^ A1_coef) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) || (^(B1_coef ^ B1_coef) !== 1'b0) ||
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(^(data_in ^ data_in) !== 1'b0) || (^(psum2_saved ^ psum2_saved) !== 1'b0))
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psum1_saved <= {psum_width{1'bx}};
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else if (init_n === 1'b0)
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psum1_saved <= {psum_width{1'b0}};
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else if (enable === 1'b1)
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psum1_saved <= psum1;
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else
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psum1_saved <= psum1_saved;
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if ((^(init_n ^ init_n) !== 1'b0) || (^(enable ^ enable) !== 1'b0) || (^(B0_coef ^ B0_coef) !== 1'b0) ||
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(^(data_in ^ data_in) !== 1'b0) || (^(psum1_saved ^ psum1_saved) !== 1'b0)) begin
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data_out_reg <= {data_out_width{1'bx}};
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saturation_reg <= 1'bx;
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end
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else if (init_n === 1'b0) begin
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data_out_reg <= {data_out_width{1'b0}};
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saturation_reg <= 1'b0;
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end
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else if (enable === 1'b1) begin
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data_out_reg <= data_out_internal;
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saturation_reg <= saturation_internal;
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end
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else begin
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data_out_reg <= data_out_reg;
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saturation_reg <= saturation_reg;
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end
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end
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else begin
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psum2_saved <= {psum_width-2{1'bx}};
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psum1_saved <= {psum_width{1'bx}};
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data_out_reg <= {data_out_width{1'bx}};
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saturation_reg <= 1'bx;
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end
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assign data_out = (out_reg == 0) ? data_out_internal : data_out_reg;
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assign saturation = (out_reg == 0) ? saturation_internal : saturation_reg;
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//-------------------------------------------------------------------------
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// Parameter legality check
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//-------------------------------------------------------------------------
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initial begin : parameter_check
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integer param_err_flg;
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param_err_flg = 0;
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if (data_in_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter data_in_width (lower bound: 2)",
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data_in_width );
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end
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if ( (data_out_width < 2) || (data_out_width > psum_width-frac_coef_width) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter data_out_width (legal range: 2 to psum_width-frac_coef_width)",
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data_out_width );
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end
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if ( (frac_data_out_width < 0) || (frac_data_out_width > data_out_width-1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter frac_data_out_width (legal range: 0 to data_out_width-1)",
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frac_data_out_width );
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end
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if (feedback_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter feedback_width (lower bound: 2)",
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feedback_width );
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end
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if (max_coef_width < 2) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter max_coef_width (lower bound: 2)",
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max_coef_width );
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end
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if ( (frac_coef_width < 0) || (frac_coef_width > max_coef_width-1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter frac_coef_width (legal range: 0 to max_coef_width-1)",
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frac_coef_width );
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end
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if ( (saturation_mode < 0) || (saturation_mode > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter saturation_mode (legal range: 0 to 1)",
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saturation_mode );
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end
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if ( (out_reg < 0) || (out_reg > 1) ) begin
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param_err_flg = 1;
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$display(
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"ERROR: %m :\n Invalid value (%d) for parameter out_reg (legal range: 0 to 1)",
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out_reg );
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end
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if ( param_err_flg == 1) begin
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$display(
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"%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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end
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end // parameter_check
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//---------------------------------------------------------------------------
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// Report unknown clock inputs
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//---------------------------------------------------------------------------
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always @ (clk) begin : clk_monitor
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if ( (clk !== 1'b0) && (clk !== 1'b1) && ($time > 0) )
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$display( "WARNING: %m :\n at time = %t, detected unknown value, %b, on clk input.",
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$time, clk );
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end // clk_monitor
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// synopsys translate_on
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endmodule
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