237 lines
6.4 KiB
Verilog
237 lines
6.4 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : TailCorr_top.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.3 2024-05-15 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module diff_p_ref
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(
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input rstn
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,input clk
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,input en
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,input vldi
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,input signed [15:0] din0
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,input signed [15:0] din1
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,input signed [15:0] din2
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,input signed [15:0] din3
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,output vldo
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,output signed [15:0] dout_p0
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,output signed [15:0] dout_p1
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,output signed [15:0] dout_p2
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,output signed [15:0] dout_p3
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,output signed [15:0] dout_p4
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,output signed [15:0] dout_p5
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,output signed [15:0] dout_p6
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,output signed [15:0] dout_p7
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,output signed [15:0] diff_p0
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,output signed [15:0] diff_p1
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,output signed [15:0] diff_p2
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,output signed [15:0] diff_p3
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,output signed [15:0] diff_p4
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,output signed [15:0] diff_p5
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,output signed [15:0] diff_p6
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,output signed [15:0] diff_p7
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);
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wire signed [15:0] din_p0_r0;
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wire signed [15:0] din_p1_r0;
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wire signed [15:0] din_p2_r0;
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wire signed [15:0] din_p3_r0;
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wire signed [15:0] din_p4_r0;
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wire signed [15:0] din_p5_r0;
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wire signed [15:0] din_p6_r0;
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wire signed [15:0] din_p7_r0;
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s2p_2_ref inst1_s2p_2_ref (
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.clk (clk),
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.rst_n (rstn),
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.din (din0),
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.en (vldi),
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.dout0 (din_p0_r0),
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.dout1 (din_p4_r0)
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,.vldo( vldo)
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);
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s2p_2_ref inst2_s2p_2_ref (
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.clk (clk),
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.rst_n (rstn),
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.din (din1),
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.en (vldi),
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.dout0 (din_p1_r0),
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.dout1 (din_p5_r0)
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,.vldo( )
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);
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s2p_2_ref inst3_s2p_2_ref (
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.clk (clk),
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.rst_n (rstn),
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.din (din2),
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.en (vldi),
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.dout0 (din_p2_r0),
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.dout1 (din_p6_r0)
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,.vldo( )
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);
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s2p_2_ref inst4_s2p_2_ref (
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.clk (clk),
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.rst_n (rstn),
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.din (din3),
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.en (vldi),
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.dout0 (din_p3_r0),
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.dout1 (din_p7_r0)
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,.vldo( )
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);
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reg signed [15:0] din_p0_r1;
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reg signed [15:0] din_p1_r1;
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reg signed [15:0] din_p2_r1;
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reg signed [15:0] din_p3_r1;
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reg signed [15:0] din_p4_r1;
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reg signed [15:0] din_p5_r1;
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reg signed [15:0] din_p6_r1;
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reg signed [15:0] din_p7_r1;
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always @(posedge clk or negedge rstn)
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if (!rstn)
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begin
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din_p0_r1 <= 'h0;
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din_p1_r1 <= 'h0;
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din_p2_r1 <= 'h0;
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din_p3_r1 <= 'h0;
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din_p4_r1 <= 'h0;
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din_p5_r1 <= 'h0;
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din_p6_r1 <= 'h0;
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din_p7_r1 <= 'h0;
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end
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else if(en)
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begin
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din_p0_r1 <= din_p0_r0;
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din_p1_r1 <= din_p1_r0;
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din_p2_r1 <= din_p2_r0;
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din_p3_r1 <= din_p3_r0;
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din_p4_r1 <= din_p4_r0;
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din_p5_r1 <= din_p5_r0;
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din_p6_r1 <= din_p6_r0;
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din_p7_r1 <= din_p7_r0;
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end
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else
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begin
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din_p0_r1 <= din_p0_r1;
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din_p1_r1 <= din_p1_r1;
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din_p2_r1 <= din_p2_r1;
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din_p3_r1 <= din_p3_r1;
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din_p4_r1 <= din_p4_r1;
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din_p5_r1 <= din_p5_r1;
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din_p6_r1 <= din_p6_r1;
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din_p7_r1 <= din_p7_r1;
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end
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assign dout_p0 = din_p0_r1;
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assign dout_p1 = din_p1_r1;
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assign dout_p2 = din_p2_r1;
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assign dout_p3 = din_p3_r1;
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assign dout_p4 = din_p4_r1;
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assign dout_p5 = din_p5_r1;
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assign dout_p6 = din_p6_r1;
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assign dout_p7 = din_p7_r1;
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wire signed [15:0] diff_p0_r0;
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wire signed [15:0] diff_p1_r0;
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wire signed [15:0] diff_p2_r0;
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wire signed [15:0] diff_p3_r0;
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wire signed [15:0] diff_p4_r0;
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wire signed [15:0] diff_p5_r0;
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wire signed [15:0] diff_p6_r0;
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wire signed [15:0] diff_p7_r0;
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assign diff_p0_r0 = din_p0_r0 - din_p7_r1;
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assign diff_p1_r0 = din_p1_r0 - din_p0_r0;
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assign diff_p2_r0 = din_p2_r0 - din_p1_r0;
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assign diff_p3_r0 = din_p3_r0 - din_p2_r0;
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assign diff_p4_r0 = din_p4_r0 - din_p3_r0;
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assign diff_p5_r0 = din_p5_r0 - din_p4_r0;
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assign diff_p6_r0 = din_p6_r0 - din_p5_r0;
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assign diff_p7_r0 = din_p7_r0 - din_p6_r0;
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reg signed [15:0] diff_p0_r1;
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reg signed [15:0] diff_p1_r1;
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reg signed [15:0] diff_p2_r1;
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reg signed [15:0] diff_p3_r1;
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reg signed [15:0] diff_p4_r1;
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reg signed [15:0] diff_p5_r1;
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reg signed [15:0] diff_p6_r1;
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reg signed [15:0] diff_p7_r1;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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diff_p0_r1 <= 0;
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diff_p1_r1 <= 0;
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diff_p2_r1 <= 0;
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diff_p3_r1 <= 0;
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diff_p4_r1 <= 0;
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diff_p5_r1 <= 0;
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diff_p6_r1 <= 0;
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diff_p7_r1 <= 0;
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end
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else if(en)begin
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diff_p0_r1 <= diff_p0_r0;
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diff_p1_r1 <= diff_p1_r0;
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diff_p2_r1 <= diff_p2_r0;
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diff_p3_r1 <= diff_p3_r0;
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diff_p4_r1 <= diff_p4_r0;
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diff_p5_r1 <= diff_p5_r0;
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diff_p6_r1 <= diff_p6_r0;
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diff_p7_r1 <= diff_p7_r0;
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end
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else begin
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diff_p0_r1 <= diff_p0_r1;
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diff_p1_r1 <= diff_p1_r1;
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diff_p2_r1 <= diff_p2_r1;
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diff_p3_r1 <= diff_p3_r1;
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diff_p4_r1 <= diff_p4_r1;
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diff_p5_r1 <= diff_p5_r1;
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diff_p6_r1 <= diff_p6_r1;
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diff_p7_r1 <= diff_p7_r1;
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end
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end
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assign diff_p0 = diff_p0_r1;
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assign diff_p1 = diff_p1_r1;
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assign diff_p2 = diff_p2_r1;
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assign diff_p3 = diff_p3_r1;
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assign diff_p4 = diff_p4_r1;
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assign diff_p5 = diff_p5_r1;
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assign diff_p6 = diff_p6_r1;
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assign diff_p7 = diff_p7_r1;
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endmodule
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