58 lines
2.2 KiB
Coq
58 lines
2.2 KiB
Coq
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : syncer.v
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// Department :
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// Author : PWY
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-03-13 PWY AWG dedicated register file
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// 0.2 2024-05-13 PWY
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module syncer # (
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parameter width = 1
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,parameter stage = 2
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)
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(
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input clk_d
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,input rstn_d
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,input [width-1:0] data_s
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,output [width-1:0] data_d
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);
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generate
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genvar i;
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wire [width-1:0] data_temp[stage-1:0];
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sirv_gnrl_dffr #(width) data_temp0_dffr (data_s ,data_temp[0], clk_d, rstn_d);
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for(i=1;i<stage;i=i+1) begin: SYNCER
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sirv_gnrl_dffr #(width) data_tempn0_dffr (data_temp[i-1] ,data_temp[i], clk_d, rstn_d);
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end
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endgenerate
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assign data_d = data_temp[stage-1];
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endmodule |