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拖尾矫正
18 Commits 4 Branches 0 Tags 22 MiB
Verilog 80.6%
SystemVerilog 13.1%
MATLAB 3.5%
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Makefile 1.1%
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thfu 2861f02533 Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ 2025-02-26 15:50:49 +08:00
edf v01-add round module;intp8 and mult_C using round;Modify the directory structure 2024-11-26 13:34:17 +08:00
rtl Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ 2025-02-26 15:50:49 +08:00
script_m Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ 2025-02-26 15:50:49 +08:00
sim Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ 2025-02-26 15:50:49 +08:00
tb Á½Â·²¢ÐеÄIIRÂ˲¨Æ÷£¬ÏÂÒ»²½¸ÄÖÁ°Ë·²¢ÐÐ 2025-02-26 15:50:49 +08:00