173 lines
3.8 KiB
Verilog
173 lines
3.8 KiB
Verilog
// Relese History
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// Version Date Author Description
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// 0.2 2024-06-14 ZYZ
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords : receive data from spi_master,sent data to PC
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// set reset to output Rdata_PC
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module rx_sram(
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input clk,
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input rstn,
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(* mark_debug="true" *) input [31:0] din ,
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(* mark_debug="true" *) input din_vld ,
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(* mark_debug="true" *) input data_rden_rx,
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(* mark_debug="true" *) output [31:0] Rdata_PC
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);
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parameter width = 32 ;
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parameter depth = 65536 ;
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//=================================================
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function integer clog2(input integer depth);
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begin
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for(clog2=0;depth>0;clog2=clog2+1)
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depth =depth>>1;
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end
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endfunction
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//=================================================
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localparam aw = clog2(depth-1);
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//=================================================
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//wr&rd address
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(* mark_debug="true" *) reg [aw-1:0] cnta ;
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(* mark_debug="true" *) reg [aw-1:0] cntb ;
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(* mark_debug="true" *) reg ena ;
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(* mark_debug="true" *) reg enb ;
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(* mark_debug="true" *) wire [31:0] doutb ;
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(* mark_debug="true" *) reg [31:0] din_reg;
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn ) begin
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din_reg <= 1'b0;
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end
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else begin
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din_reg <= din;
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end
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end
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(* mark_debug="true" *) reg data_rden_rx_reg;
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn) begin
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data_rden_rx_reg <= 1'b0 ;
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end
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else begin
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data_rden_rx_reg <= data_rden_rx ;
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end
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end
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//addra addrb
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn) begin
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cnta <= 'h0 ;
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end
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else if(ena) begin
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cnta <= cnta + 'b1;
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end
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else
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cnta <= cnta ;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn ) begin
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cntb <= 'h0;
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end
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else if(enb) begin
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cntb <= cntb + 'b1;
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end
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else begin
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cntb <= cntb;
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end
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end
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//enable
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn ) begin
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ena <= 1'b0;
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end
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else begin
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ena <= din_vld;
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end
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end
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn) begin
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enb <= 1'b0 ;
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end
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else if(data_rden_rx_reg & (cntb <= cnta - 1'b1))begin
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enb <= 1'b1 ;
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end
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else begin
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enb <= 1'b0 ;
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end
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end
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reg [31:0] Rdata_PC_reg;
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always @(posedge clk or negedge rstn)
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begin
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if(!rstn ) begin
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Rdata_PC_reg <= 32'b0;
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end
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else begin
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Rdata_PC_reg <= doutb;
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end
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end
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assign Rdata_PC = Rdata_PC_reg;
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/*
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blk_mem_gen_0 blk_mem_gen_0_inst(
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.clka(clk),
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.ena(1'b1),
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.wea(ena),
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.dina(Rdata_reg),
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.addra(cnta),
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.clkb(clk),
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.enb(enb),
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.doutb(doutb),
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.addrb(cntb)
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);
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*/
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spram_model #(
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.width(width),
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.depth(depth)
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)spram_inst(
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.clka(clk),
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.ena(~ena),
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.dina(din_reg),
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.addra(cnta),
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.clkb(clk),
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.enb(~enb),
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.doutb(doutb),
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.addrb(cntb)
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);
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endmodule
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