77 lines
2.1 KiB
Coq
77 lines
2.1 KiB
Coq
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : diff.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-05-11 thfu
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module diff(
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clk,
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rstn,
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en,
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din,
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dout
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);
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input rstn;
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input clk;
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input en;
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input signed [15:0] din;
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output signed [15:0] dout;
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reg [15:0] din_r;
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reg [15:0] din_r1;
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reg [15:0] out_r;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_r <= 16'd0;
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din_r1 <= 16'd0;
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out_r <= 16'd0;
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end
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else if(en)
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begin
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din_r <= din;
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din_r1 <= din_r;
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out_r <= din_r - din_r1;
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end
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else
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begin
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din_r <= din_r;
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din_r1 <= din_r1;
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out_r <= out_r;
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end
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assign dout = out_r;
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endmodule
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