380 lines
12 KiB
Verilog
380 lines
12 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
|
|
// Company:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// File Name : TailCorr_top.v
|
|
// Department :
|
|
// Author : thfu
|
|
// Author's Tel :
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Relese History
|
|
// Version Date Author Description
|
|
// 0.3 2024-05-15 thfu
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Keywords :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Parameter
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Purpose :
|
|
//
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Target Device:
|
|
// Tool versions:
|
|
//-----------------------------------------------------------------------------------------------------------------
|
|
// Reuse Issues
|
|
// Reset Strategy:
|
|
// Clock Domains:
|
|
// Critical Timing:
|
|
// Asynchronous I/F:
|
|
// Synthesizable (y/n):
|
|
// Other:
|
|
//-FHDR--------------------------------------------------------------------------------------------------------
|
|
|
|
module IIR_top_ref
|
|
|
|
(
|
|
input rstn
|
|
,input clk
|
|
,input en
|
|
,input signed [15:0] IIRin_p0
|
|
,input signed [15:0] IIRin_p1
|
|
,input signed [15:0] IIRin_p2
|
|
,input signed [15:0] IIRin_p3
|
|
,input signed [15:0] IIRin_p4
|
|
,input signed [15:0] IIRin_p5
|
|
,input signed [15:0] IIRin_p6
|
|
,input signed [15:0] IIRin_p7
|
|
,input signed [31 :0] a_re
|
|
,input signed [31 :0] a_im
|
|
,input signed [31 :0] ab_re
|
|
,input signed [31 :0] ab_im
|
|
,input signed [31 :0] abb_re
|
|
,input signed [31 :0] abb_im
|
|
,input signed [31 :0] ab_pow3_re
|
|
,input signed [31 :0] ab_pow3_im
|
|
,input signed [31 :0] ab_pow4_re
|
|
,input signed [31 :0] ab_pow4_im
|
|
,input signed [31 :0] ab_pow5_re
|
|
,input signed [31 :0] ab_pow5_im
|
|
,input signed [31 :0] ab_pow6_re
|
|
,input signed [31 :0] ab_pow6_im
|
|
,input signed [31 :0] ab_pow7_re
|
|
,input signed [31 :0] ab_pow7_im
|
|
,input signed [31 :0] b_pow8_re
|
|
,input signed [31 :0] b_pow8_im
|
|
|
|
,output signed [15:0] IIRout_p0
|
|
,output signed [15:0] IIRout_p1
|
|
,output signed [15:0] IIRout_p2
|
|
,output signed [15:0] IIRout_p3
|
|
,output signed [15:0] IIRout_p4
|
|
,output signed [15:0] IIRout_p5
|
|
,output signed [15:0] IIRout_p6
|
|
,output signed [15:0] IIRout_p7
|
|
);
|
|
|
|
reg signed [15:0] IIRin_p0_r1;
|
|
reg signed [15:0] IIRin_p1_r1;
|
|
reg signed [15:0] IIRin_p2_r1;
|
|
reg signed [15:0] IIRin_p3_r1;
|
|
reg signed [15:0] IIRin_p4_r1;
|
|
reg signed [15:0] IIRin_p5_r1;
|
|
reg signed [15:0] IIRin_p6_r1;
|
|
reg signed [15:0] IIRin_p7_r1;
|
|
always @(posedge clk or negedge rstn)
|
|
if (!rstn)
|
|
begin
|
|
IIRin_p0_r1 <= 'h0;
|
|
IIRin_p1_r1 <= 'h0;
|
|
IIRin_p2_r1 <= 'h0;
|
|
IIRin_p3_r1 <= 'h0;
|
|
IIRin_p4_r1 <= 'h0;
|
|
IIRin_p5_r1 <= 'h0;
|
|
IIRin_p6_r1 <= 'h0;
|
|
IIRin_p7_r1 <= 'h0;
|
|
end
|
|
else if(en)
|
|
begin
|
|
IIRin_p0_r1 <= IIRin_p0;
|
|
IIRin_p1_r1 <= IIRin_p1;
|
|
IIRin_p2_r1 <= IIRin_p2;
|
|
IIRin_p3_r1 <= IIRin_p3;
|
|
IIRin_p4_r1 <= IIRin_p4;
|
|
IIRin_p5_r1 <= IIRin_p5;
|
|
IIRin_p6_r1 <= IIRin_p6;
|
|
IIRin_p7_r1 <= IIRin_p7;
|
|
end
|
|
else
|
|
begin
|
|
IIRin_p0_r1 <= IIRin_p0_r1;
|
|
IIRin_p1_r1 <= IIRin_p1_r1;
|
|
IIRin_p2_r1 <= IIRin_p2_r1;
|
|
IIRin_p3_r1 <= IIRin_p3_r1;
|
|
IIRin_p4_r1 <= IIRin_p4_r1;
|
|
IIRin_p5_r1 <= IIRin_p5_r1;
|
|
IIRin_p6_r1 <= IIRin_p6_r1;
|
|
IIRin_p7_r1 <= IIRin_p7_r1;
|
|
end
|
|
|
|
IIR_Filter_p8_ref inst_iir_0_p0 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p0 ),
|
|
.dinp1 (IIRin_p7_r1 ),
|
|
.dinp2 (IIRin_p6_r1 ),
|
|
.dinp3 (IIRin_p5_r1 ),
|
|
.dinp4 (IIRin_p4_r1 ),
|
|
.dinp5 (IIRin_p3_r1 ),
|
|
.dinp6 (IIRin_p2_r1 ),
|
|
.dinp7 (IIRin_p1_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p0 )
|
|
);
|
|
|
|
IIR_Filter_p8_ref inst_iir_o_p1 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p1 ),
|
|
.dinp1 (IIRin_p0 ),
|
|
.dinp2 (IIRin_p7_r1 ),
|
|
.dinp3 (IIRin_p6_r1 ),
|
|
.dinp4 (IIRin_p5_r1 ),
|
|
.dinp5 (IIRin_p4_r1 ),
|
|
.dinp6 (IIRin_p3_r1 ),
|
|
.dinp7 (IIRin_p2_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p1 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p2 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p2 ),
|
|
.dinp1 (IIRin_p1 ),
|
|
.dinp2 (IIRin_p0 ),
|
|
.dinp3 (IIRin_p7_r1 ),
|
|
.dinp4 (IIRin_p6_r1 ),
|
|
.dinp5 (IIRin_p5_r1 ),
|
|
.dinp6 (IIRin_p4_r1 ),
|
|
.dinp7 (IIRin_p3_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p2 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p3 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p3 ),
|
|
.dinp1 (IIRin_p2 ),
|
|
.dinp2 (IIRin_p1 ),
|
|
.dinp3 (IIRin_p0 ),
|
|
.dinp4 (IIRin_p7_r1 ),
|
|
.dinp5 (IIRin_p6_r1 ),
|
|
.dinp6 (IIRin_p5_r1 ),
|
|
.dinp7 (IIRin_p4_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p3 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p4 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p4 ),
|
|
.dinp1 (IIRin_p3 ),
|
|
.dinp2 (IIRin_p2 ),
|
|
.dinp3 (IIRin_p1 ),
|
|
.dinp4 (IIRin_p0 ),
|
|
.dinp5 (IIRin_p7_r1 ),
|
|
.dinp6 (IIRin_p6_r1 ),
|
|
.dinp7 (IIRin_p5_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p4 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p5 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p5 ),
|
|
.dinp1 (IIRin_p4 ),
|
|
.dinp2 (IIRin_p3 ),
|
|
.dinp3 (IIRin_p2 ),
|
|
.dinp4 (IIRin_p1 ),
|
|
.dinp5 (IIRin_p0 ),
|
|
.dinp6 (IIRin_p7_r1 ),
|
|
.dinp7 (IIRin_p6_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p5 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p6 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p6 ),
|
|
.dinp1 (IIRin_p5 ),
|
|
.dinp2 (IIRin_p4 ),
|
|
.dinp3 (IIRin_p3 ),
|
|
.dinp4 (IIRin_p2 ),
|
|
.dinp5 (IIRin_p1 ),
|
|
.dinp6 (IIRin_p0 ),
|
|
.dinp7 (IIRin_p7_r1 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p6 )
|
|
);
|
|
IIR_Filter_p8_ref inst_iir_0_p7 (
|
|
.clk (clk ),
|
|
.rstn (rstn ),
|
|
.en (en ),
|
|
.dinp0 (IIRin_p7 ),
|
|
.dinp1 (IIRin_p6 ),
|
|
.dinp2 (IIRin_p5 ),
|
|
.dinp3 (IIRin_p4 ),
|
|
.dinp4 (IIRin_p3 ),
|
|
.dinp5 (IIRin_p2 ),
|
|
.dinp6 (IIRin_p1 ),
|
|
.dinp7 (IIRin_p0 ),
|
|
.a_re (a_re ),
|
|
.a_im (a_im ),
|
|
.ab_re (ab_re ),
|
|
.ab_im (ab_im ),
|
|
.abb_re (abb_re ),
|
|
.abb_im (abb_im ),
|
|
.ab_pow3_re (ab_pow3_re ),
|
|
.ab_pow3_im (ab_pow3_im ),
|
|
.ab_pow4_re (ab_pow4_re ),
|
|
.ab_pow4_im (ab_pow4_im ),
|
|
.ab_pow5_re (ab_pow5_re ),
|
|
.ab_pow5_im (ab_pow5_im ),
|
|
.ab_pow6_re (ab_pow6_re ),
|
|
.ab_pow6_im (ab_pow6_im ),
|
|
.ab_pow7_re (ab_pow7_re ),
|
|
.ab_pow7_im (ab_pow7_im ),
|
|
.b_pow8_re (b_pow8_re ),
|
|
.b_pow8_im (b_pow8_im ),
|
|
.dout (IIRout_p7 )
|
|
);
|
|
|
|
endmodule
|
|
|