217 lines
6.4 KiB
Verilog
217 lines
6.4 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : MeanIntp_8.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.1 2024-09-27 thfu top module of 8 mean interpolation
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module MeanIntp_8(
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clk,
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rstn,
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en,
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intp_mode,
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din, //input
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dout_0,//output
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dout_1,
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dout_2,
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dout_3,
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dout_4,
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dout_5,
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dout_6,
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dout_7
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);
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input rstn;
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input clk;
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input en;
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input [1:0] intp_mode;
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input signed [15:0] din;
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output signed [15:0] dout_0;
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output signed [15:0] dout_1;
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output signed [15:0] dout_2;
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output signed [15:0] dout_3;
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output signed [15:0] dout_4;
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output signed [15:0] dout_5;
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output signed [15:0] dout_6;
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output signed [15:0] dout_7;
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reg [15:0] din_r1;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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din_r1 <= 'h0;
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end
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else if(en)
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begin
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din_r1 <= din;
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end
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else
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begin
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din_r1 <= din_r1;
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end
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wire [16:0] sum_0_1;
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assign sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};
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wire signed [16:0] diff_1_2;//(din-din_r1)/2
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wire signed [16:0] diff_1_4;//(din-din_r1)/4
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wire signed [16:0] diff_1_8;//(din-din_r1)/8
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assign diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]};
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assign diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]};
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assign diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]};
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reg signed [16:0] dout_r0;
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reg signed [16:0] dout_r1;
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reg signed [16:0] dout_r2;
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reg signed [16:0] dout_r3;
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reg signed [16:0] dout_r4;
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reg signed [16:0] dout_r5;
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reg signed [16:0] dout_r6;
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reg signed [16:0] dout_r7;
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always@(posedge clk or negedge rstn)
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if(!rstn)
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begin
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dout_r0 <= 'h0;
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dout_r1 <= 'h0;
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dout_r2 <= 'h0;
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dout_r3 <= 'h0;
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dout_r4 <= 'h0;
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dout_r5 <= 'h0;
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dout_r6 <= 'h0;
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dout_r7 <= 'h0;
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end
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else if(en)
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begin
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dout_r0 <= din_r1;
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dout_r1 <= din_r1 + diff_1_8;
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dout_r2 <= din_r1 + diff_1_4;
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dout_r3 <= din_r1 + diff_1_4 + diff_1_8;
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dout_r4 <= din_r1 + diff_1_2;
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dout_r5 <= din_r1 + diff_1_2 + diff_1_8;
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dout_r6 <= din_r1 + diff_1_2 + diff_1_4;
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dout_r7 <= din_r1 + diff_1_2 + diff_1_4 + diff_1_8;
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end
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else
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begin
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dout_r0 <= dout_r0;
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dout_r1 <= dout_r1;
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dout_r2 <= dout_r2;
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dout_r3 <= dout_r3;
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dout_r4 <= dout_r4;
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dout_r5 <= dout_r5;
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dout_r6 <= dout_r6;
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dout_r7 <= dout_r7;
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end
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reg signed [15:0] mux_p_0;
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reg signed [15:0] mux_p_1;
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reg signed [15:0] mux_p_2;
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reg signed [15:0] mux_p_3;
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reg signed [15:0] mux_p_4;
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reg signed [15:0] mux_p_5;
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reg signed [15:0] mux_p_6;
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reg signed [15:0] mux_p_7;
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always@(posedge clk) begin
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case(intp_mode)
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2'b00:
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begin
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mux_p_0 <= dout_r0;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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end
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2'b01:
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begin
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mux_p_0 <= dout_r0;
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mux_p_1 <= dout_r4;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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end
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2'b10:
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begin
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mux_p_0 <= dout_r0;
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mux_p_1 <= dout_r2;
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mux_p_2 <= dout_r4;
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mux_p_3 <= dout_r6;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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end
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2'b11:
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begin
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mux_p_0 <= dout_r0;
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mux_p_1 <= dout_r1;
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mux_p_2 <= dout_r2;
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mux_p_3 <= dout_r3;
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mux_p_4 <= dout_r4;
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mux_p_5 <= dout_r5;
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mux_p_6 <= dout_r6;
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mux_p_7 <= dout_r7;
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end
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default:
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begin
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mux_p_0 <= 16'h0;
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mux_p_1 <= 16'h0;
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mux_p_2 <= 16'h0;
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mux_p_3 <= 16'h0;
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mux_p_4 <= 16'h0;
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mux_p_5 <= 16'h0;
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mux_p_6 <= 16'h0;
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mux_p_7 <= 16'h0;
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end
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endcase
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end
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assign dout_0 = mux_p_0[15:0];
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assign dout_1 = mux_p_1[15:0];
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assign dout_2 = mux_p_2[15:0];
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assign dout_3 = mux_p_3[15:0];
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assign dout_4 = mux_p_4[15:0];
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assign dout_5 = mux_p_5[15:0];
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assign dout_6 = mux_p_6[15:0];
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assign dout_7 = mux_p_7[15:0];
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endmodule
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