thfu 038ab149bc v04-add valid output port and convert from 8 to 4		2024-11-14 20:35:56 +08:00
..
nco	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
DW02_mult.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
DW_iir_dc.v	v04-IIR based on IP core	2024-11-09 17:13:18 +08:00
DW_mult_pipe.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
IIR_Filter.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
MeanIntp_8.v	v04-MeanIntp_8.v work with enable	2024-11-14 20:32:29 +08:00
TailCorr_top.v	v04-add valid output port and convert from 8 to 4	2024-11-14 20:35:56 +08:00
diff.v	v04-enable of clk_div2	2024-11-12 17:35:22 +08:00
lsdacif.v	modify relevant .v file and .m file to verify the accuracy of rtl code	2024-10-17 17:29:11 +08:00
mult_C.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
z_data_mux.v	add 8 interpolation	2024-10-08 11:24:32 +08:00
z_dsp.edf	v04-z_dsp on FPGA	2024-11-12 20:03:17 +08:00
z_dsp.v	v04-add valid output port and convert from 8 to 4	2024-11-14 20:35:56 +08:00
z_dsp_en_Test.edf	v04-enable of clk_div2	2024-11-12 17:35:22 +08:00
z_dsp_en_Test.v	v04-add valid output port and convert from 8 to 4	2024-11-14 20:35:56 +08:00
z_dsp_wrapper.v	v04-add valid output port and convert from 8 to 4	2024-11-14 20:35:56 +08:00