327 lines
7.1 KiB
Verilog
327 lines
7.1 KiB
Verilog
/*
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Copyright 2018-2020 Nuclei System Technology, Inc.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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//=====================================================================
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//
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// Designer : Bob Hu
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//
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// Description:
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// All of the general DFF and Latch modules
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//
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// ====================================================================
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//
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//
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is 1
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//
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// ===========================================================================
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`define DISABLE_SV_ASSERTION
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`define dly #0.2
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module sirv_gnrl_dfflrs # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLRS_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b1}};
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is 0
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//
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// ===========================================================================
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module sirv_gnrl_dfflr # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLR_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b0}};
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable and Reset
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// Default reset value is input
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//
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// ===========================================================================
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module sirv_gnrl_dfflrd # (
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parameter DW = 32
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) (
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input [DW-1:0] init,
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFLR_PROC
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if (rst_n == 1'b0)
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qout_r <= init;
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else if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Load-enable, no reset
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//
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// ===========================================================================
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module sirv_gnrl_dffl # (
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parameter DW = 32
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) (
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk)
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begin : DFFL_PROC
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if (lden == 1'b1)
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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sirv_gnrl_xchecker # (
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.DW(1)
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) sirv_gnrl_xchecker(
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.i_dat(lden),
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.clk (clk)
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);
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Reset, no load-enable
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// Default reset value is 1
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//
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// ===========================================================================
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module sirv_gnrl_dffrs # (
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parameter DW = 32
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) (
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFRS_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b1}};
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else
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module sirv_gnrl DFF with Reset, no load-enable
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// Default reset value is 0
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//
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// ===========================================================================
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module sirv_gnrl_dffr # (
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parameter DW = 32
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) (
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input clk,
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input rst_n
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);
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reg [DW-1:0] qout_r;
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always @(posedge clk or negedge rst_n)
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begin : DFFR_PROC
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if (rst_n == 1'b0)
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qout_r <= {DW{1'b0}};
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else
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qout_r <= `dly dnxt;
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end
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assign qout = qout_r;
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endmodule
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// ===========================================================================
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//
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// Description:
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// Verilog module for general latch
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//
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// ===========================================================================
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module sirv_gnrl_ltch # (
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parameter DW = 32
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) (
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//input test_mode,
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input lden,
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input [DW-1:0] dnxt,
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output [DW-1:0] qout
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);
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reg [DW-1:0] qout_r;
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always @ *
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begin : LTCH_PROC
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if (lden == 1'b1)
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qout_r <= dnxt;
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end
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//assign qout = test_mode ? dnxt : qout_r;
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assign qout = qout_r;
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`ifndef FPGA_SOURCE//{
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`ifndef DISABLE_SV_ASSERTION//{
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//synopsys translate_off
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always_comb
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begin
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CHECK_THE_X_VALUE:
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assert (lden !== 1'bx)
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else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
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end
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//synopsys translate_on
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`endif//}
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`endif//}
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endmodule
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