312 lines
10 KiB
Verilog
312 lines
10 KiB
Verilog
//+FHDR--------------------------------------------------------------------------------------------------------
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// Company:
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//-----------------------------------------------------------------------------------------------------------------
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// File Name : IIR_Filter.v
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// Department :
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// Author : thfu
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// Author's Tel :
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//-----------------------------------------------------------------------------------------------------------------
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// Relese History
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// Version Date Author Description
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// 0.4 2024-05-28 thfu
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//2024-05-28 10:22:49
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//-----------------------------------------------------------------------------------------------------------------
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// Keywords :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Parameter
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Purpose :
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//
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//-----------------------------------------------------------------------------------------------------------------
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// Target Device:
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// Tool versions:
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//-----------------------------------------------------------------------------------------------------------------
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// Reuse Issues
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// Reset Strategy:
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// Clock Domains:
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// Critical Timing:
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// Asynchronous I/F:
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// Synthesizable (y/n):
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// Other:
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//-FHDR--------------------------------------------------------------------------------------------------------
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module CoefGen #(
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parameter data_in_width = 32
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,parameter coef_width = 32
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,parameter frac_data_out_width = 20//X for in,5
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,parameter frac_coef_width = 31//division
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)
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(
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input rstn
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,input clk
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,input [5:0] vldi
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,input signed [coef_width-1 :0] a_re [5:0]
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,input signed [coef_width-1 :0] a_im [5:0]
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,input signed [coef_width-1 :0] b_re [5:0]
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,input signed [coef_width-1 :0] b_im [5:0]
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,output reg signed [coef_width-1 :0] ao_re [5:0]
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,output reg signed [coef_width-1 :0] ao_im [5:0]
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,output reg signed [coef_width-1 :0] ab_re [5:0]
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,output reg signed [coef_width-1 :0] ab_im [5:0]
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,output reg signed [coef_width-1 :0] abb_re [5:0]
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,output reg signed [coef_width-1 :0] abb_im [5:0]
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,output reg signed [coef_width-1 :0] ab_pow3_re [5:0]
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,output reg signed [coef_width-1 :0] ab_pow3_im [5:0]
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,output reg signed [coef_width-1 :0] ab_pow4_re [5:0]
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,output reg signed [coef_width-1 :0] ab_pow4_im [5:0]
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,output reg signed [coef_width-1 :0] ab_pow5_re [5:0]
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,output reg signed [coef_width-1 :0] ab_pow5_im [5:0]
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,output reg signed [coef_width-1 :0] ab_pow6_re [5:0]
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,output reg signed [coef_width-1 :0] ab_pow6_im [5:0]
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,output reg signed [coef_width-1 :0] ab_pow7_re [5:0]
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,output reg signed [coef_width-1 :0] ab_pow7_im [5:0]
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,output reg signed [coef_width-1 :0] b_pow8_re [5:0]
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,output reg signed [coef_width-1 :0] b_pow8_im [5:0]
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);
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reg [5:0] vldi_r1;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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vldi_r1 <= 'h0;
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end
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else if(vldi)begin
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vldi_r1 <= vldi;
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end
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end
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reg vldi_or_r1;
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wire vldi_or = | vldi;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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vldi_or_r1 <= 'h0;
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end
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else begin
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vldi_or_r1 <= vldi_or;
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end
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end
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reg signed [data_in_width-1:0] a_re_r1;
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reg signed [data_in_width-1:0] a_im_r1;
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reg signed [data_in_width-1:0] b_re_r1;
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reg signed [data_in_width-1:0] b_im_r1;
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genvar i;
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generate
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for (i = 0; i < 6; i = i + 1) begin
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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a_re_r1 <= 'h0;
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a_im_r1 <= 'h0;
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b_re_r1 <= 'h0;
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b_im_r1 <= 'h0;
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end
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else if(vldi[i]) begin
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a_re_r1 <= a_re[i];
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a_im_r1 <= a_im[i];
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b_re_r1 <= b_re[i];
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b_im_r1 <= b_im[i];
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end
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else begin
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a_re_r1 <= a_re_r1;
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a_im_r1 <= a_im_r1;
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b_re_r1 <= b_re_r1;
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b_im_r1 <= b_im_r1;
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end
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end
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end
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endgenerate
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reg en;
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reg en_r1;
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reg en_r2;
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reg [3:0] cnt0;
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wire add_cnt0;
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wire end_cnt0;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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cnt0 <= 0;
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end
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else if(add_cnt0)begin
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if(end_cnt0)
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cnt0 <= 0;
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else
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cnt0 <= cnt0 + 1;
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end
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end
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assign add_cnt0 = en;
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assign end_cnt0 = add_cnt0 && cnt0== 8-1;
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wire en_l;
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wire en_h;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en <= 0;
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end
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else if(en_h)begin
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en <= 1;
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end
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else if(en_l)begin
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en <= 0;
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end
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end
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assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
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assign en_l = end_cnt0;
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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en_r1 <= 'h0;
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en_r2 <= 'h0;
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end
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else begin
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en_r1 <= en;
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en_r2 <= en_r1;
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end
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end
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reg signed [data_in_width-1:0] bin_re;
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reg signed [data_in_width-1:0] bin_im;
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wire signed [data_in_width-1:0] bout_re;
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wire signed [data_in_width-1:0] bout_im;
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always @(*)begin
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if(en_r1) begin
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bin_re <= bout_re;
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bin_im <= bout_im;
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end
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else begin
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bin_re <= 32'd2147483647;
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bin_im <= 0;
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end
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end
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mult_C
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width)
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,.D_width(coef_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c1 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (bin_re ),
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.b (bin_im ),
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.c (b_re_r1 ),
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.d (b_im_r1 ),
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.Re (bout_re ),
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.Im (bout_im )
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);
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reg [3:1] cnt1;
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wire add_cnt1;
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wire end_cnt1;
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always @(posedge clk or negedge rstn)begin
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if(!rstn)begin
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cnt1 <= 0;
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end
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else if(add_cnt1)begin
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if(end_cnt1)
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cnt1 <= 0;
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else
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cnt1 <= cnt1 + 1;
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end
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end
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assign add_cnt1 = end_cnt0;
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assign end_cnt1 = add_cnt1 && cnt1== 7-1;
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wire signed [data_in_width-1:0] abo_re;
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wire signed [data_in_width-1:0] abo_im;
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mult_C
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#(
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.A_width(data_in_width)
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,.B_width(data_in_width)
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,.C_width(coef_width)
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,.D_width(coef_width)
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,.frac_coef_width(frac_coef_width)
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)
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inst_c2 (
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.clk (clk ),
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.rstn (rstn ),
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.en (en ),
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.a (bin_re ),
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.b (bin_im ),
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.c (a_re_r1 ),
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.d (a_im_r1 ),
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.Re (abo_re ),
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.Im (abo_im )
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);
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generate
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for (i = 0; i < 6; i = i + 1) begin
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always @(posedge clk or negedge rstn)begin
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if(rstn==1'b0)begin
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ao_re[i] <= 0;
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ao_im[i] <= 0;
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ab_re[i] <= 0;
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ab_im[i] <= 0;
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abb_re[i] <= 0;
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abb_im[i] <= 0;
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ab_pow3_re[i] <= 0;
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ab_pow3_im[i] <= 0;
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ab_pow4_re[i] <= 0;
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ab_pow4_im[i] <= 0;
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ab_pow5_re[i] <= 0;
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ab_pow5_im[i] <= 0;
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ab_pow6_re[i] <= 0;
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ab_pow6_im[i] <= 0;
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ab_pow7_re[i] <= 0;
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ab_pow7_im[i] <= 0;
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b_pow8_re[i] <= 0;
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b_pow8_im[i] <= 0;
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end
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else if(vldi_r1[i] && en_r1) begin
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if(add_cnt0 && cnt0 == 1 && en_r1)begin
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ao_re[i] <= abo_re;
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ao_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 2 && en_r1)begin
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ab_re[i] <= abo_re;
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ab_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 3 && en_r1)begin
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abb_re[i] <= abo_re;
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abb_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 4 && en_r1)begin
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ab_pow3_re[i] <= abo_re;
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ab_pow3_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 5 && en_r1)begin
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ab_pow4_re[i] <= abo_re;
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ab_pow4_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 6 && en_r1)begin
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ab_pow5_re[i] <= abo_re;
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ab_pow5_im[i] <= abo_im;
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end
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else if(add_cnt0 && cnt0 == 7 && en_r1)begin
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ab_pow6_re[i] <= abo_re;
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ab_pow6_im[i] <= abo_im;
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end
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else if(cnt0 == 0 && en_r1)begin
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ab_pow7_re[i] <= abo_re;
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ab_pow7_im[i] <= abo_im;
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b_pow8_re[i] <= bin_re;
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b_pow8_im[i] <= bin_im;
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end
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end
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// else begin
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// end
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end
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end
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endgenerate
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endmodule
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