`timescale 1 ns/1 ns module TB(); initial begin $fsdbDumpfile("TB.fsdb"); $fsdbDumpvars(0, TB); $fsdbDumpMDA(); end reg clk ; reg en; reg [5:0] vldi; reg rst_n; reg signed [31:0] a_re [5:0]; reg signed [31:0] a_im [5:0]; reg signed [31:0] b_re [5:0]; reg signed [31:0] b_im [5:0]; wire signed [31:0] ao_re [5:0]; wire signed [31:0] ao_im [5:0]; wire signed [31:0] ab_re [5:0]; wire signed [31:0] ab_im [5:0]; wire signed [31:0] abb_re [5:0]; wire signed [31:0] abb_im [5:0]; wire signed [31:0] ab_pow3_re [5:0]; wire signed [31:0] ab_pow3_im [5:0]; wire signed [31:0] ab_pow4_re [5:0]; wire signed [31:0] ab_pow4_im [5:0]; wire signed [31:0] ab_pow5_re [5:0]; wire signed [31:0] ab_pow5_im [5:0]; wire signed [31:0] ab_pow6_re [5:0]; wire signed [31:0] ab_pow6_im [5:0]; wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] ab_pow7_im [5:0]; wire signed [31:0] bo_re [5:0]; wire signed [31:0] bo_im [5:0]; wire signed [31:0] b_pow8_re [5:0]; wire signed [31:0] b_pow8_im [5:0]; parameter CYCLE = 20; parameter RST_TIME = 3 ; CoefGen inst_CoefGen( .clk (clk ), .rstn (rst_n ), .vldi (vldi ), .a0_re (a_re[0] ), .a0_im (a_im[0] ), .b0_re (b_re[0] ), .b0_im (b_im[0] ), .a1_re (a_re[1] ), .a1_im (a_im[1] ), .b1_re (b_re[1] ), .b1_im (b_im[1] ), .a2_re (a_re[2] ), .a2_im (a_im[2] ), .b2_re (b_re[2] ), .b2_im (b_im[2] ), .a3_re (a_re[3] ), .a3_im (a_im[3] ), .b3_re (b_re[3] ), .b3_im (b_im[3] ), .a4_re (a_re[4] ), .a4_im (a_im[4] ), .b4_re (b_re[4] ), .b4_im (b_im[4] ), .a5_re (a_re[5] ), .a5_im (a_im[5] ), .b5_re (b_re[5] ), .b5_im (b_im[5] ), .a_re0 (ao_re[0] ), .a_im0 (ao_im[0] ), .b_re0 (bo_re[0] ), .b_im0 (bo_im[0] ), .ab_re0 (ab_re[0] ), .ab_im0 (ab_im[0] ), .abb_re0 (abb_re[0] ), .abb_im0 (abb_im[0] ), .ab_pow3_re0 (ab_pow3_re[0]), .ab_pow3_im0 (ab_pow3_im[0]), .ab_pow4_re0 (ab_pow4_re[0]), .ab_pow4_im0 (ab_pow4_im[0]), .ab_pow5_re0 (ab_pow5_re[0]), .ab_pow5_im0 (ab_pow5_im[0]), .ab_pow6_re0 (ab_pow6_re[0]), .ab_pow6_im0 (ab_pow6_im[0]), .ab_pow7_re0 (ab_pow7_re[0]), .ab_pow7_im0 (ab_pow7_im[0]), .b_pow8_re0 (b_pow8_re[0] ), .b_pow8_im0 (b_pow8_im[0] ), .a_re1 (ao_re[1] ), .a_im1 (ao_im[1] ), .b_re1 (bo_re[1] ), .b_im1 (bo_im[1] ), .ab_re1 (ab_re[1] ), .ab_im1 (ab_im[1] ), .abb_re1 (abb_re[1] ), .abb_im1 (abb_im[1] ), .ab_pow3_re1 (ab_pow3_re[1]), .ab_pow3_im1 (ab_pow3_im[1]), .ab_pow4_re1 (ab_pow4_re[1]), .ab_pow4_im1 (ab_pow4_im[1]), .ab_pow5_re1 (ab_pow5_re[1]), .ab_pow5_im1 (ab_pow5_im[1]), .ab_pow6_re1 (ab_pow6_re[1]), .ab_pow6_im1 (ab_pow6_im[1]), .ab_pow7_re1 (ab_pow7_re[1]), .ab_pow7_im1 (ab_pow7_im[1]), .b_pow8_re1 (b_pow8_re[1] ), .b_pow8_im1 (b_pow8_im[1] ), .a_re2 (ao_re[2] ), .a_im2 (ao_im[2] ), .b_re2 (bo_re[2] ), .b_im2 (bo_im[2] ), .ab_re2 (ab_re[2] ), .ab_im2 (ab_im[2] ), .abb_re2 (abb_re[2] ), .abb_im2 (abb_im[2] ), .ab_pow3_re2 (ab_pow3_re[2]), .ab_pow3_im2 (ab_pow3_im[2]), .ab_pow4_re2 (ab_pow4_re[2]), .ab_pow4_im2 (ab_pow4_im[2]), .ab_pow5_re2 (ab_pow5_re[2]), .ab_pow5_im2 (ab_pow5_im[2]), .ab_pow6_re2 (ab_pow6_re[2]), .ab_pow6_im2 (ab_pow6_im[2]), .ab_pow7_re2 (ab_pow7_re[2]), .ab_pow7_im2 (ab_pow7_im[2]), .b_pow8_re2 (b_pow8_re[2] ), .b_pow8_im2 (b_pow8_im[2] ), .a_re3 (ao_re[3] ), .a_im3 (ao_im[3] ), .b_re3 (bo_re[3] ), .b_im3 (bo_im[3] ), .ab_re3 (ab_re[3] ), .ab_im3 (ab_im[3] ), .abb_re3 (abb_re[3] ), .abb_im3 (abb_im[3] ), .ab_pow3_re3 (ab_pow3_re[3]), .ab_pow3_im3 (ab_pow3_im[3]), .ab_pow4_re3 (ab_pow4_re[3]), .ab_pow4_im3 (ab_pow4_im[3]), .ab_pow5_re3 (ab_pow5_re[3]), .ab_pow5_im3 (ab_pow5_im[3]), .ab_pow6_re3 (ab_pow6_re[3]), .ab_pow6_im3 (ab_pow6_im[3]), .ab_pow7_re3 (ab_pow7_re[3]), .ab_pow7_im3 (ab_pow7_im[3]), .b_pow8_re3 (b_pow8_re[3] ), .b_pow8_im3 (b_pow8_im[3] ), .a_re4 (ao_re[4] ), .a_im4 (ao_im[4] ), .b_re4 (bo_re[4] ), .b_im4 (bo_im[4] ), .ab_re4 (ab_re[4] ), .ab_im4 (ab_im[4] ), .abb_re4 (abb_re[4] ), .abb_im4 (abb_im[4] ), .ab_pow3_re4 (ab_pow3_re[4]), .ab_pow3_im4 (ab_pow3_im[4]), .ab_pow4_re4 (ab_pow4_re[4]), .ab_pow4_im4 (ab_pow4_im[4]), .ab_pow5_re4 (ab_pow5_re[4]), .ab_pow5_im4 (ab_pow5_im[4]), .ab_pow6_re4 (ab_pow6_re[4]), .ab_pow6_im4 (ab_pow6_im[4]), .ab_pow7_re4 (ab_pow7_re[4]), .ab_pow7_im4 (ab_pow7_im[4]), .b_pow8_re4 (b_pow8_re[4] ), .b_pow8_im4 (b_pow8_im[4] ), .a_re5 (ao_re[5] ), .a_im5 (ao_im[5] ), .b_re5 (bo_re[5] ), .b_im5 (bo_im[5] ), .ab_re5 (ab_re[5] ), .ab_im5 (ab_im[5] ), .abb_re5 (abb_re[5] ), .abb_im5 (abb_im[5] ), .ab_pow3_re5 (ab_pow3_re[5]), .ab_pow3_im5 (ab_pow3_im[5]), .ab_pow4_re5 (ab_pow4_re[5]), .ab_pow4_im5 (ab_pow4_im[5]), .ab_pow5_re5 (ab_pow5_re[5]), .ab_pow5_im5 (ab_pow5_im[5]), .ab_pow6_re5 (ab_pow6_re[5]), .ab_pow6_im5 (ab_pow6_im[5]), .ab_pow7_re5 (ab_pow7_re[5]), .ab_pow7_im5 (ab_pow7_im[5]), .b_pow8_re5 (b_pow8_re[5] ), .b_pow8_im5 (b_pow8_im[5] ) ); initial begin clk = 0; forever #(CYCLE/2) clk=~clk; end reg [15:0] st1; reg [15:0] st2; reg [15:0] st3; reg [15:0] st4; initial begin rst_n = 0; vldi <= 0; st1 = 100; st2 = 101; st3 = 110; st4 = 111; repeat(3) @(posedge clk); vldi[0] <= 1; rst_n = 1; a_re[0] <= 55007237; a_im[0] <= 0; b_re[0] <= 2143083068; b_im[0] <= 0; @(posedge clk); vldi[0] <= 0; a_re[0] <= 0; a_im[0] <= 0; b_re[0] <= 0; b_im[0] <= 0; repeat(8) @(posedge clk); vldi[1] <= 1; rst_n = 1; a_re[1] <= 32690030; a_im[1] <= 0; b_re[1] <= 2145807236; b_im[1] <= 0; @(posedge clk); vldi[1] <= 0; a_re[1] <= 0; a_im[1] <= 0; b_re[1] <= 0; b_im[1] <= 0; repeat(8) @(posedge clk); vldi[2] <= 1; rst_n = 1; a_re[2] <= 429516; a_im[2] <= 0; b_re[2] <= 2146812530; b_im[2] <= 0; @(posedge clk); vldi[2] <= 0; a_re[2] <= 0; a_im[2] <= 0; b_re[2] <= 0; b_im[2] <= 0; end reg [21:0] cnt; always@(posedge clk or negedge rst_n) if(!rst_n) begin cnt <= 22'd0; end else begin cnt <= cnt + 22'd1; end initial begin wait(cnt[16]==1'b1) $finish(0); end endmodule