`timescale 1 ns/1 ns

module TB();
initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
     $fsdbDumpMDA();
end



reg clk  ;
reg en;
reg [5:0] vldi;
reg rst_n;


reg signed [31:0] a_re  [5:0];
reg signed [31:0] a_im  [5:0];
reg signed [31:0] b_re  [5:0];
reg signed [31:0] b_im  [5:0];


wire signed [31:0] ao_re         [5:0];
wire signed [31:0] ao_im         [5:0];
wire signed [31:0] ab_re         [5:0];
wire signed [31:0] ab_im         [5:0];
wire signed [31:0] abb_re        [5:0];
wire signed [31:0] abb_im        [5:0];
wire signed [31:0] ab_pow3_re    [5:0];
wire signed [31:0] ab_pow3_im    [5:0];
wire signed [31:0] ab_pow4_re    [5:0];
wire signed [31:0] ab_pow4_im    [5:0];
wire signed [31:0] ab_pow5_re    [5:0];
wire signed [31:0] ab_pow5_im    [5:0];
wire signed [31:0] ab_pow6_re    [5:0];
wire signed [31:0] ab_pow6_im    [5:0];
wire signed [31:0] ab_pow7_re    [5:0];
wire signed [31:0] ab_pow7_im    [5:0];
wire signed [31:0] b_pow8_re     [5:0];
wire signed [31:0] b_pow8_im     [5:0];

        
parameter CYCLE    = 20;


parameter RST_TIME = 3 ;


CoefGen uut(
    .clk               (clk          ), 
    .rstn              (rst_n        ),
    .vldi              (vldi         ),
    .a_re              (a_re         ),
    .a_im              (a_im         ),
    .b_re              (b_re         ),
    .b_im              (b_im         ),
    .ao_re             (ao_re       ),
    .ao_im             (ao_im       ),
    .ab_re             (ab_re        ),
    .ab_im             (ab_im        ),
    .abb_re            (abb_re       ),
    .abb_im            (abb_im       ),
    .ab_pow3_re        (ab_pow3_re   ),
    .ab_pow3_im        (ab_pow3_im   ),
    .ab_pow4_re        (ab_pow4_re   ),
    .ab_pow4_im        (ab_pow4_im   ),
    .ab_pow5_re        (ab_pow5_re   ),
    .ab_pow5_im        (ab_pow5_im   ),
    .ab_pow6_re        (ab_pow6_re   ),
    .ab_pow6_im        (ab_pow6_im   ),
    .ab_pow7_re        (ab_pow7_re   ),
    .ab_pow7_im        (ab_pow7_im   ),
    .b_pow8_re         (b_pow8_re    ),
    .b_pow8_im         (b_pow8_im    )
    );


            
initial begin
    clk = 0;
    forever
    #(CYCLE/2)
    clk=~clk;
end
reg [15:0]  st1;
reg [15:0]  st2;
reg [15:0]  st3;
reg [15:0]  st4;
            
initial begin
    rst_n = 0;
    vldi <= 0;
    st1 = 100;
    st2 = 101;
    st3 = 110;
    st4 = 111;
    repeat(3) @(posedge clk);
        vldi[0] <= 1; 
        rst_n = 1;
        a_re[0]     <=      55007237;
        a_im[0]     <=      0;
        b_re[0]     <=      2143083068;
        b_im[0]     <=      0;
    @(posedge clk);
        vldi[0] <= 0; 
        a_re[0]     <=      0;
        a_im[0]     <=      0;
        b_re[0]     <=      0;
        b_im[0]     <=      0;
    repeat(8) @(posedge clk);
        vldi[1] <= 1; 
        rst_n = 1;
        a_re[1]     <=      32690030;
        a_im[1]     <=      0;
        b_re[1]     <=      2145807236;
        b_im[1]     <=      0;
    @(posedge clk);
        vldi[1] <= 0; 
        a_re[1]     <=      0;
        a_im[1]     <=      0;
        b_re[1]     <=      0;
        b_im[1]     <=      0;
    repeat(8) @(posedge clk);
        vldi[2] <= 1; 
        rst_n = 1;
        a_re[2]     <=      429516;
        a_im[2]     <=      0;
        b_re[2]     <=      2146812530;
        b_im[2]     <=      0;
    @(posedge clk);
        vldi[2] <= 0; 
        a_re[2]     <=      0;
        a_im[2]     <=      0;
        b_re[2]     <=      0;
        b_im[2]     <=      0;

end

            
reg     [21:0]  cnt;
always@(posedge clk or negedge rst_n)
                if(!rst_n) begin
                        cnt     <=      22'd0;
                end
                else  begin
                        cnt     <=      cnt + 22'd1;
                end

initial 
begin
        wait(cnt[16]==1'b1)
                        $finish(0);
end




endmodule