module  CoefGen #(
 parameter  data_in_width       = 32 
,parameter  coef_width          = 32 
,parameter  frac_data_out_width = 20//X for in,5
,parameter  frac_coef_width     = 31//division
)
(
 input	 rstn
,input	 clk
,input	 [5:0] vldi  
,input  signed [31:0]   a0_re            
,input  signed [31:0]   a0_im            
,input  signed [31:0]   b0_re            
,input  signed [31:0]   b0_im            
,input  signed [31:0]   a1_re            
,input  signed [31:0]   a1_im            
,input  signed [31:0]   b1_re            
,input  signed [31:0]   b1_im            
,input  signed [31:0]   a2_re            
,input  signed [31:0]   a2_im            
,input  signed [31:0]   b2_re            
,input  signed [31:0]   b2_im            
,input  signed [31:0]   a3_re            
,input  signed [31:0]   a3_im            
,input  signed [31:0]   b3_re            
,input  signed [31:0]   b3_im            
,input  signed [31:0]   a4_re            
,input  signed [31:0]   a4_im            
,input  signed [31:0]   b4_re            
,input  signed [31:0]   b4_im            
,input  signed [31:0]   a5_re            
,input  signed [31:0]   a5_im            
,input  signed [31:0]   b5_re            
,input  signed [31:0]   b5_im            
,output reg signed [31:0]   a_re0
,output reg signed [31:0]   a_im0
,output reg signed [31:0]   ab_re0
,output reg signed [31:0]   ab_im0
,output reg signed [31:0]   abb_re0
,output reg signed [31:0]   abb_im0
,output reg signed [31:0]   ab_pow3_re0
,output reg signed [31:0]   ab_pow3_im0
,output reg signed [31:0]   ab_pow4_re0
,output reg signed [31:0]   ab_pow4_im0
,output reg signed [31:0]   ab_pow5_re0
,output reg signed [31:0]   ab_pow5_im0
,output reg signed [31:0]   ab_pow6_re0
,output reg signed [31:0]   ab_pow6_im0
,output reg signed [31:0]   ab_pow7_re0
,output reg signed [31:0]   ab_pow7_im0
,output reg signed [31:0]   b_pow8_re0
,output reg signed [31:0]   b_pow8_im0
,output reg signed [31:0]   a_re1
,output reg signed [31:0]   a_im1
,output reg signed [31:0]   ab_re1
,output reg signed [31:0]   ab_im1
,output reg signed [31:0]   abb_re1
,output reg signed [31:0]   abb_im1
,output reg signed [31:0]   ab_pow3_re1
,output reg signed [31:0]   ab_pow3_im1
,output reg signed [31:0]   ab_pow4_re1
,output reg signed [31:0]   ab_pow4_im1
,output reg signed [31:0]   ab_pow5_re1
,output reg signed [31:0]   ab_pow5_im1
,output reg signed [31:0]   ab_pow6_re1
,output reg signed [31:0]   ab_pow6_im1
,output reg signed [31:0]   ab_pow7_re1
,output reg signed [31:0]   ab_pow7_im1
,output reg signed [31:0]   b_pow8_re1
,output reg signed [31:0]   b_pow8_im1
,output reg signed [31:0]   a_re2
,output reg signed [31:0]   a_im2
,output reg signed [31:0]   ab_re2
,output reg signed [31:0]   ab_im2
,output reg signed [31:0]   abb_re2
,output reg signed [31:0]   abb_im2
,output reg signed [31:0]   ab_pow3_re2
,output reg signed [31:0]   ab_pow3_im2
,output reg signed [31:0]   ab_pow4_re2
,output reg signed [31:0]   ab_pow4_im2
,output reg signed [31:0]   ab_pow5_re2
,output reg signed [31:0]   ab_pow5_im2
,output reg signed [31:0]   ab_pow6_re2
,output reg signed [31:0]   ab_pow6_im2
,output reg signed [31:0]   ab_pow7_re2
,output reg signed [31:0]   ab_pow7_im2
,output reg signed [31:0]   b_pow8_re2
,output reg signed [31:0]   b_pow8_im2
,output reg signed [31:0]   a_re3
,output reg signed [31:0]   a_im3
,output reg signed [31:0]   ab_re3
,output reg signed [31:0]   ab_im3
,output reg signed [31:0]   abb_re3
,output reg signed [31:0]   abb_im3
,output reg signed [31:0]   ab_pow3_re3
,output reg signed [31:0]   ab_pow3_im3
,output reg signed [31:0]   ab_pow4_re3
,output reg signed [31:0]   ab_pow4_im3
,output reg signed [31:0]   ab_pow5_re3
,output reg signed [31:0]   ab_pow5_im3
,output reg signed [31:0]   ab_pow6_re3
,output reg signed [31:0]   ab_pow6_im3
,output reg signed [31:0]   ab_pow7_re3
,output reg signed [31:0]   ab_pow7_im3
,output reg signed [31:0]   b_pow8_re3
,output reg signed [31:0]   b_pow8_im3
,output reg signed [31:0]   a_re4
,output reg signed [31:0]   a_im4
,output reg signed [31:0]   ab_re4
,output reg signed [31:0]   ab_im4
,output reg signed [31:0]   abb_re4
,output reg signed [31:0]   abb_im4
,output reg signed [31:0]   ab_pow3_re4
,output reg signed [31:0]   ab_pow3_im4
,output reg signed [31:0]   ab_pow4_re4
,output reg signed [31:0]   ab_pow4_im4
,output reg signed [31:0]   ab_pow5_re4
,output reg signed [31:0]   ab_pow5_im4
,output reg signed [31:0]   ab_pow6_re4
,output reg signed [31:0]   ab_pow6_im4
,output reg signed [31:0]   ab_pow7_re4
,output reg signed [31:0]   ab_pow7_im4
,output reg signed [31:0]   b_pow8_re4
,output reg signed [31:0]   b_pow8_im4
,output reg signed [31:0]   a_re5
,output reg signed [31:0]   a_im5
,output reg signed [31:0]   ab_re5
,output reg signed [31:0]   ab_im5
,output reg signed [31:0]   abb_re5
,output reg signed [31:0]   abb_im5
,output reg signed [31:0]   ab_pow3_re5
,output reg signed [31:0]   ab_pow3_im5
,output reg signed [31:0]   ab_pow4_re5
,output reg signed [31:0]   ab_pow4_im5
,output reg signed [31:0]   ab_pow5_re5
,output reg signed [31:0]   ab_pow5_im5
,output reg signed [31:0]   ab_pow6_re5
,output reg signed [31:0]   ab_pow6_im5
,output reg signed [31:0]   ab_pow7_re5
,output reg signed [31:0]   ab_pow7_im5
,output reg signed [31:0]   b_pow8_re5
,output reg signed [31:0]   b_pow8_im5
);


reg   vldi_or_r1;
wire  vldi_or = | vldi;  
sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi_or, vldi_or_r1 ,clk,rstn); 

reg 	signed	[data_in_width-1:0]    a_re_r1;
reg 	signed	[data_in_width-1:0]    a_im_r1;
reg 	signed	[data_in_width-1:0]    b_re_r1;
reg 	signed	[data_in_width-1:0]    b_im_r1;

always @(posedge clk or negedge rstn) begin
    if(rstn == 1'b0) begin
        a_re_r1 <= 'h0;
        a_im_r1 <= 'h0;
        b_re_r1 <= 'h0;
        b_im_r1 <= 'h0;
    end
    else if(|vldi) begin  
        case(1'b1)
            vldi[0]: begin
                a_re_r1 <= a0_re;
                a_im_r1 <= a0_im;
                b_re_r1 <= b0_re;
                b_im_r1 <= b0_im;
            end
            vldi[1]: begin
                a_re_r1 <= a1_re;
                a_im_r1 <= a1_im;
                b_re_r1 <= b1_re;
                b_im_r1 <= b1_im;
            end
            vldi[2]: begin
                a_re_r1 <= a2_re;
                a_im_r1 <= a2_im;
                b_re_r1 <= b2_re;
                b_im_r1 <= b2_im;
            end
            vldi[3]: begin
                a_re_r1 <= a3_re;
                a_im_r1 <= a3_im;
                b_re_r1 <= b3_re;
                b_im_r1 <= b3_im;
            end
            vldi[4]: begin
                a_re_r1 <= a4_re;
                a_im_r1 <= a4_im;
                b_re_r1 <= b4_re;
                b_im_r1 <= b4_im;
            end
            vldi[5]: begin
                a_re_r1 <= a5_re;
                a_im_r1 <= a5_im;
                b_re_r1 <= b5_re;
                b_im_r1 <= b5_im;
            end
//            default: begin
//                a_re_r1 <= a_re[0];
//                a_im_r1 <= a_im[0];
//                b_re_r1 <= b_re[0];
//                b_im_r1 <= b_im[0];
//            end
        endcase
    end
end

reg en;
reg en_r1;
sirv_gnrl_dffr #(1) dff_en_1(en, en_r1 ,clk,rstn);

reg [3:0] cnt0;
wire add_cnt0;
wire end_cnt0;
always @(posedge clk or negedge rstn)begin
    if(!rstn)begin
        cnt0 <= 0;
    end
    else if(add_cnt0)begin
        if(end_cnt0)
            cnt0 <= 0;
        else
            cnt0 <= cnt0 + 1;
    end
end

assign add_cnt0 = en;
assign end_cnt0 = add_cnt0 && cnt0== 8-1;

wire    en_l;
wire    en_h;
always  @(posedge clk or negedge rstn)begin
    if(rstn==1'b0)begin
        en <= 0;
    end
    else if(en_h)begin
        en <= 1;
    end
    else if(en_l)begin
        en <= 0;
    end
end

assign    en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0;
assign    en_l = end_cnt0;

reg 	signed	[data_in_width-1:0]   bin_re;
reg 	signed	[data_in_width-1:0]   bin_im;
wire 	signed	[data_in_width-1:0]   bout_re;
wire 	signed	[data_in_width-1:0]   bout_im;
always  @(*)begin
    if(en_r1) begin
        bin_re <= bout_re;
        bin_im <= bout_im;
    end
    else  begin
        bin_re <= 32'd2147483647;
        bin_im <= 0;
    end
end

mult_C
#(
 .A_width(data_in_width) 
,.B_width(data_in_width) 
,.C_width(coef_width) 
,.D_width(coef_width) 
,.frac_coef_width(frac_coef_width) 
)
inst_c1         (
                                            .clk	(clk    	),
                                            .rstn	(rstn   	),
                                            .en		(en     	),
                                            .a		(bin_re		),
                                            .b		(bin_im		),
                                            .c		(b_re_r1    	),
                                            .d		(b_im_r1    	),
                                            .Re		(bout_re     	),
                                            .Im		(bout_im     	)
		);

 
wire	signed	[data_in_width-1:0] 	 abo_re;
wire	signed	[data_in_width-1:0]	 abo_im;
mult_C
#(
 .A_width(data_in_width) 
,.B_width(data_in_width) 
,.C_width(coef_width) 
,.D_width(coef_width) 
,.frac_coef_width(frac_coef_width) 
)
inst_c2         (
                                            .clk	(clk    	),
                                            .rstn	(rstn   	),
                                            .en		(en     	),
                                            .a		(bin_re		),
                                            .b		(bin_im		),
                                            .c		(a_re_r1        ),
                                            .d		(a_im_r1        ),
                                            .Re		(abo_re   	),
                                            .Im		(abo_im   	)
	        );

reg signed	[coef_width-1   :0]   ao_re_r1             ;
reg signed	[coef_width-1   :0]   ao_im_r1             ;
reg signed	[coef_width-1   :0]   ab_re_r1             ;
reg signed	[coef_width-1   :0]   ab_im_r1             ;
reg signed	[coef_width-1   :0]   abb_re_r1            ;
reg signed	[coef_width-1   :0]   abb_im_r1            ;
reg signed	[coef_width-1   :0]   ab_pow3_re_r1        ;
reg signed	[coef_width-1   :0]   ab_pow3_im_r1        ;
reg signed	[coef_width-1   :0]   ab_pow4_re_r1        ;
reg signed	[coef_width-1   :0]   ab_pow4_im_r1        ;
reg signed	[coef_width-1   :0]   ab_pow5_re_r1        ;
reg signed	[coef_width-1   :0]   ab_pow5_im_r1        ;
reg signed	[coef_width-1   :0]   ab_pow6_re_r1        ;
reg signed	[coef_width-1   :0]   ab_pow6_im_r1        ;
reg signed	[coef_width-1   :0]   ab_pow7_re_r1        ;
reg signed	[coef_width-1   :0]   ab_pow7_im_r1        ;
reg signed	[coef_width-1   :0]   b_pow8_re_r1         ;
reg signed	[coef_width-1   :0]   b_pow8_im_r1         ;

always  @(posedge clk or negedge rstn)begin
    if(rstn==1'b0)begin
        ao_re_r1      <= 0;   
        ao_im_r1      <= 0;   
        ab_re_r1      <= 0;   
        ab_im_r1      <= 0;   
        abb_re_r1     <= 0;   
        abb_im_r1     <= 0;   
        ab_pow3_re_r1 <= 0;   
        ab_pow3_im_r1 <= 0;   
        ab_pow4_re_r1 <= 0;   
        ab_pow4_im_r1 <= 0;   
        ab_pow5_re_r1 <= 0;   
        ab_pow5_im_r1 <= 0;   
        ab_pow6_re_r1 <= 0;   
        ab_pow6_im_r1 <= 0;   
        ab_pow7_re_r1 <= 0;   
        ab_pow7_im_r1 <= 0;   
        b_pow8_re_r1  <= 0;   
        b_pow8_im_r1  <= 0;   
    end
    else if(add_cnt0 && cnt0 == 1 && en_r1)begin
        ao_re_r1      <= abo_re;   
        ao_im_r1      <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 2 && en_r1)begin
        ab_re_r1      <= abo_re;   
        ab_im_r1      <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 3 && en_r1)begin
        abb_re_r1      <= abo_re;   
        abb_im_r1      <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 4 && en_r1)begin
        ab_pow3_re_r1     <= abo_re;   
        ab_pow3_im_r1     <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 5 && en_r1)begin
        ab_pow4_re_r1     <= abo_re;   
        ab_pow4_im_r1     <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 6 && en_r1)begin
        ab_pow5_re_r1     <= abo_re;   
        ab_pow5_im_r1     <= abo_im;   
    end
    else if(add_cnt0 && cnt0 == 7 && en_r1)begin
        ab_pow6_re_r1     <= abo_re;   
        ab_pow6_im_r1     <= abo_im;   
    end
    else if(cnt0 == 0 && en_r1)begin
        ab_pow7_re_r1     <= abo_re;   
        ab_pow7_im_r1     <= abo_im;   
        b_pow8_re_r1     <= bin_re;   
        b_pow8_im_r1     <= bin_im;   
    end
//            else  begin
//            end
end

reg  [5:0]  vldi_r1;
reg  [5:0]  vldi_r2;
reg  [5:0]  vldi_r3;
reg  [5:0]  vldi_r4;
reg  [5:0]  vldi_r5;
reg  [5:0]  vldi_r6;
reg  [5:0]  vldi_r7;
reg  [5:0]  vldi_r8;
reg  [5:0]  vldi_r9;
reg  [5:0]  vldi_r10;
//syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10);     
sirv_gnrl_dffr #(6) dff_vldi_1(vldi,vldi_r1,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_2(vldi_r1, vldi_r2 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_3(vldi_r2, vldi_r3 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_4(vldi_r3, vldi_r4 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_5(vldi_r4, vldi_r5 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_6(vldi_r5, vldi_r6 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_7(vldi_r6, vldi_r7 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_8(vldi_r7, vldi_r8 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_9(vldi_r8, vldi_r9 ,clk,rstn); 
sirv_gnrl_dffr #(6) dff_vldi_10(vldi_r9, vldi_r10,clk,rstn); 
always @(posedge clk or negedge rstn) begin
    if(rstn == 1'b0) begin
        a_re0        <= 0;
        a_im0        <= 0;
        ab_re0       <= 0;
        ab_im0       <= 0;
        abb_re0      <= 0;
        abb_im0      <= 0;
        ab_pow3_re0  <= 0;
        ab_pow3_im0  <= 0;
        ab_pow4_re0  <= 0;
        ab_pow4_im0  <= 0;
        ab_pow5_re0  <= 0;
        ab_pow5_im0  <= 0;
        ab_pow6_re0  <= 0;
        ab_pow6_im0  <= 0;
        ab_pow7_re0  <= 0;
        ab_pow7_im0  <= 0;
        b_pow8_re0   <= 0;
        b_pow8_im0   <= 0;
        a_re1        <= 0;
        a_im1        <= 0;
        ab_re1       <= 0;
        ab_im1       <= 0;
        abb_re1      <= 0;
        abb_im1      <= 0;
        ab_pow3_re1  <= 0;
        ab_pow3_im1  <= 0;
        ab_pow4_re1  <= 0;
        ab_pow4_im1  <= 0;
        ab_pow5_re1  <= 0;
        ab_pow5_im1  <= 0;
        ab_pow6_re1  <= 0;
        ab_pow6_im1  <= 0;
        ab_pow7_re1  <= 0;
        ab_pow7_im1  <= 0;
        b_pow8_re1   <= 0;
        b_pow8_im1   <= 0;
        a_re2        <= 0;
        a_im2        <= 0;
        ab_re2       <= 0;
        ab_im2       <= 0;
        abb_re2      <= 0;
        abb_im2      <= 0;
        ab_pow3_re2  <= 0;
        ab_pow3_im2  <= 0;
        ab_pow4_re2  <= 0;
        ab_pow4_im2  <= 0;
        ab_pow5_re2  <= 0;
        ab_pow5_im2  <= 0;
        ab_pow6_re2  <= 0;
        ab_pow6_im2  <= 0;
        ab_pow7_re2  <= 0;
        ab_pow7_im2  <= 0;
        b_pow8_re2   <= 0;
        b_pow8_im2   <= 0;
        a_re3        <= 0;
        a_im3        <= 0;
        ab_re3       <= 0;
        ab_im3       <= 0;
        abb_re3      <= 0;
        abb_im3      <= 0;
        ab_pow3_re3  <= 0;
        ab_pow3_im3  <= 0;
        ab_pow4_re3  <= 0;
        ab_pow4_im3  <= 0;
        ab_pow5_re3  <= 0;
        ab_pow5_im3  <= 0;
        ab_pow6_re3  <= 0;
        ab_pow6_im3  <= 0;
        ab_pow7_re3  <= 0;
        ab_pow7_im3  <= 0;
        b_pow8_re3   <= 0;
        b_pow8_im3   <= 0;
        a_re4        <= 0;
        a_im4        <= 0;
        ab_re4       <= 0;
        ab_im4       <= 0;
        abb_re4      <= 0;
        abb_im4      <= 0;
        ab_pow3_re4  <= 0;
        ab_pow3_im4  <= 0;
        ab_pow4_re4  <= 0;
        ab_pow4_im4  <= 0;
        ab_pow5_re4  <= 0;
        ab_pow5_im4  <= 0;
        ab_pow6_re4  <= 0;
        ab_pow6_im4  <= 0;
        ab_pow7_re4  <= 0;
        ab_pow7_im4  <= 0;
        b_pow8_re4   <= 0;
        b_pow8_im4   <= 0;
        a_re5        <= 0;
        a_im5        <= 0;
        ab_re5       <= 0;
        ab_im5       <= 0;
        abb_re5      <= 0;
        abb_im5      <= 0;
        ab_pow3_re5  <= 0;
        ab_pow3_im5  <= 0;
        ab_pow4_re5  <= 0;
        ab_pow4_im5  <= 0;
        ab_pow5_re5  <= 0;
        ab_pow5_im5  <= 0;
        ab_pow6_re5  <= 0;
        ab_pow6_im5  <= 0;
        ab_pow7_re5  <= 0;
        ab_pow7_im5  <= 0;
        b_pow8_re5   <= 0;
        b_pow8_im5   <= 0;
    end
    else if(|vldi_r10) begin  
        case(1'b1)
            vldi_r10[0]: begin
                a_re0        <= ao_re_r1     ;
                a_im0        <= ao_im_r1     ;
                ab_re0       <= ab_re_r1     ;
                ab_im0       <= ab_im_r1     ;
                abb_re0      <= abb_re_r1    ;
                abb_im0      <= abb_im_r1    ;
                ab_pow3_re0  <= ab_pow3_re_r1;
                ab_pow3_im0  <= ab_pow3_im_r1;
                ab_pow4_re0  <= ab_pow4_re_r1;
                ab_pow4_im0  <= ab_pow4_im_r1;
                ab_pow5_re0  <= ab_pow5_re_r1;
                ab_pow5_im0  <= ab_pow5_im_r1;
                ab_pow6_re0  <= ab_pow6_re_r1;
                ab_pow6_im0  <= ab_pow6_im_r1;
                ab_pow7_re0  <= ab_pow7_re_r1;
                ab_pow7_im0  <= ab_pow7_im_r1;
                b_pow8_re0   <= b_pow8_re_r1 ;
                b_pow8_im0   <= b_pow8_im_r1 ;
            end
            vldi_r10[1]: begin
                a_re1        <= ao_re_r1     ;
                a_im1        <= ao_im_r1     ;
                ab_re1       <= ab_re_r1     ;
                ab_im1       <= ab_im_r1     ;
                abb_re1      <= abb_re_r1    ;
                abb_im1      <= abb_im_r1    ;
                ab_pow3_re1  <= ab_pow3_re_r1;
                ab_pow3_im1  <= ab_pow3_im_r1;
                ab_pow4_re1  <= ab_pow4_re_r1;
                ab_pow4_im1  <= ab_pow4_im_r1;
                ab_pow5_re1  <= ab_pow5_re_r1;
                ab_pow5_im1  <= ab_pow5_im_r1;
                ab_pow6_re1  <= ab_pow6_re_r1;
                ab_pow6_im1  <= ab_pow6_im_r1;
                ab_pow7_re1  <= ab_pow7_re_r1;
                ab_pow7_im1  <= ab_pow7_im_r1;
                b_pow8_re1   <= b_pow8_re_r1 ;
                b_pow8_im1   <= b_pow8_im_r1 ;
            end
            vldi_r10[2]: begin
                a_re2        <= ao_re_r1     ;
                a_im2        <= ao_im_r1     ;
                ab_re2       <= ab_re_r1     ;
                ab_im2       <= ab_im_r1     ;
                abb_re2      <= abb_re_r1    ;
                abb_im2      <= abb_im_r1    ;
                ab_pow3_re2  <= ab_pow3_re_r1;
                ab_pow3_im2  <= ab_pow3_im_r1;
                ab_pow4_re2  <= ab_pow4_re_r1;
                ab_pow4_im2  <= ab_pow4_im_r1;
                ab_pow5_re2  <= ab_pow5_re_r1;
                ab_pow5_im2  <= ab_pow5_im_r1;
                ab_pow6_re2  <= ab_pow6_re_r1;
                ab_pow6_im2  <= ab_pow6_im_r1;
                ab_pow7_re2  <= ab_pow7_re_r1;
                ab_pow7_im2  <= ab_pow7_im_r1;
                b_pow8_re2   <= b_pow8_re_r1 ;
                b_pow8_im2   <= b_pow8_im_r1 ;
            end
            vldi_r10[3]: begin
                a_re3        <= ao_re_r1     ;
                a_im3        <= ao_im_r1     ;
                ab_re3       <= ab_re_r1     ;
                ab_im3       <= ab_im_r1     ;
                abb_re3      <= abb_re_r1    ;
                abb_im3      <= abb_im_r1    ;
                ab_pow3_re3  <= ab_pow3_re_r1;
                ab_pow3_im3  <= ab_pow3_im_r1;
                ab_pow4_re3  <= ab_pow4_re_r1;
                ab_pow4_im3  <= ab_pow4_im_r1;
                ab_pow5_re3  <= ab_pow5_re_r1;
                ab_pow5_im3  <= ab_pow5_im_r1;
                ab_pow6_re3  <= ab_pow6_re_r1;
                ab_pow6_im3  <= ab_pow6_im_r1;
                ab_pow7_re3  <= ab_pow7_re_r1;
                ab_pow7_im3  <= ab_pow7_im_r1;
                b_pow8_re3   <= b_pow8_re_r1 ;
                b_pow8_im3   <= b_pow8_im_r1 ;
            end
            vldi_r10[4]: begin
                a_re4        <= ao_re_r1     ;
                a_im4        <= ao_im_r1     ;
                ab_re4       <= ab_re_r1     ;
                ab_im4       <= ab_im_r1     ;
                abb_re4      <= abb_re_r1    ;
                abb_im4      <= abb_im_r1    ;
                ab_pow3_re4  <= ab_pow3_re_r1;
                ab_pow3_im4  <= ab_pow3_im_r1;
                ab_pow4_re4  <= ab_pow4_re_r1;
                ab_pow4_im4  <= ab_pow4_im_r1;
                ab_pow5_re4  <= ab_pow5_re_r1;
                ab_pow5_im4  <= ab_pow5_im_r1;
                ab_pow6_re4  <= ab_pow6_re_r1;
                ab_pow6_im4  <= ab_pow6_im_r1;
                ab_pow7_re4  <= ab_pow7_re_r1;
                ab_pow7_im4  <= ab_pow7_im_r1;
                b_pow8_re4   <= b_pow8_re_r1 ;
                b_pow8_im4   <= b_pow8_im_r1 ;
            end
            vldi_r10[5]: begin
                a_re5        <= ao_re_r1     ;
                a_im5        <= ao_im_r1     ;
                ab_re5       <= ab_re_r1     ;
                ab_im5       <= ab_im_r1     ;
                abb_re5      <= abb_re_r1    ;
                abb_im5      <= abb_im_r1    ;
                ab_pow3_re5  <= ab_pow3_re_r1;
                ab_pow3_im5  <= ab_pow3_im_r1;
                ab_pow4_re5  <= ab_pow4_re_r1;
                ab_pow4_im5  <= ab_pow4_im_r1;
                ab_pow5_re5  <= ab_pow5_re_r1;
                ab_pow5_im5  <= ab_pow5_im_r1;
                ab_pow6_re5  <= ab_pow6_re_r1;
                ab_pow6_im5  <= ab_pow6_im_r1;
                ab_pow7_re5  <= ab_pow7_re_r1;
                ab_pow7_im5  <= ab_pow7_im_r1;
                b_pow8_re5   <= b_pow8_re_r1 ;
                b_pow8_im5   <= b_pow8_im_r1 ;
            end
//            default: begin
//                ao_re[0]       <= 'h0;
//                ao_im[0]       <= 'h0;
//                ab_re[0]       <= 'h0;
//                ab_im[0]       <= 'h0;
//                abb_re[0]      <= 'h0;
//                abb_im[0]      <= 'h0;
//                ab_pow3_re[0]  <= 'h0;
//                ab_pow3_im[0]  <= 'h0;
//                ab_pow4_re[0]  <= 'h0;
//                ab_pow4_im[0]  <= 'h0;
//                ab_pow5_re[0]  <= 'h0;
//                ab_pow5_im[0]  <= 'h0;
//                ab_pow6_re[0]  <= 'h0;
//                ab_pow6_im[0]  <= 'h0;
//                ab_pow7_re[0]  <= 'h0;
//                ab_pow7_im[0]  <= 'h0;
//                b_pow8_re[0]   <= 'h0;
//                b_pow8_im[0]   <= 'h0;
//            end
        endcase
    end
end

endmodule