module 	diff_p	 	

(
 input rstn
,input clk
,input  en
,input  vldi 
,input  signed [15:0] din0
,input  signed [15:0] din1
,input  signed [15:0] din2
,input  signed [15:0] din3
,output               vldo 
,output  signed	[15:0] dout_p0
,output  signed	[15:0] dout_p1
,output  signed	[15:0] dout_p2
,output  signed	[15:0] dout_p3
,output  signed	[15:0] dout_p4
,output  signed	[15:0] dout_p5
,output  signed	[15:0] dout_p6
,output  signed	[15:0] dout_p7
,output  signed	[15:0] diff_p0
,output  signed	[15:0] diff_p1
,output  signed	[15:0] diff_p2
,output  signed	[15:0] diff_p3
,output  signed	[15:0] diff_p4
,output  signed	[15:0] diff_p5
,output  signed	[15:0] diff_p6
,output  signed	[15:0] diff_p7

		 	);		

wire  signed  [15:0]  din_p0_r0;
wire  signed  [15:0]  din_p1_r0;
wire  signed  [15:0]  din_p2_r0;
wire  signed  [15:0]  din_p3_r0;
wire  signed  [15:0]  din_p4_r0;
wire  signed  [15:0]  din_p5_r0;
wire  signed  [15:0]  din_p6_r0;
wire  signed  [15:0]  din_p7_r0;
wire  vldo_0;
wire  vldo_1;
wire  vldo_2;
wire  vldo_3;
wire  vldo_r0;
assign  vldo_r0  =  vldo_0 || vldo_1 || vldo_2 || vldo_3; 
sirv_gnrl_dffr #(1) dff_vldo_1(vldo_r0, vldo ,clk,rstn);
s2p_2 inst1_s2p_2 (
        .clk    (clk),
        .rst_n  (rstn),
        .din    (din0),
        .en   (vldi),
        .dout0 (din_p0_r0),
        .dout1 (din_p4_r0)
        ,.vldo( vldo_0)
    );
s2p_2 inst2_s2p_2 (
        .clk    (clk),
        .rst_n  (rstn),
        .din    (din1),
        .en   (vldi),
        .dout0 (din_p1_r0),
        .dout1 (din_p5_r0)
        ,.vldo( vldo_1)
    );
s2p_2 inst3_s2p_2 (
        .clk    (clk),
        .rst_n  (rstn),
        .din    (din2),
        .en   (vldi),
        .dout0 (din_p2_r0),
        .dout1 (din_p6_r0)
        ,.vldo( vldo_2)
    );
s2p_2 inst4_s2p_2 (
        .clk    (clk),
        .rst_n  (rstn),
        .din    (din3),
        .en   (vldi),
        .dout0 (din_p3_r0),
        .dout1 (din_p7_r0)
        ,.vldo( vldo_3)
    );


wire  signed [15:0]		    din_p0_r1;
wire  signed [15:0]		    din_p1_r1;
wire  signed [15:0]		    din_p2_r1;
wire  signed [15:0]		    din_p3_r1;
wire  signed [15:0]		    din_p4_r1;
wire  signed [15:0]		    din_p5_r1;
wire  signed [15:0]		    din_p6_r1;
wire  signed [15:0]		    din_p7_r1;

sirv_gnrl_dfflr #(16) din_p7_1(en,din_p7_r0, din_p7_r1 ,clk,rstn);

assign  dout_p0 = din_p0_r0;
assign  dout_p1 = din_p1_r0;
assign  dout_p2 = din_p2_r0;
assign  dout_p3 = din_p3_r0;
assign  dout_p4 = din_p4_r0;
assign  dout_p5 = din_p5_r0;
assign  dout_p6 = din_p6_r0;
assign  dout_p7 = din_p7_r0;

reg signed [15:0] diff_p0_r1;
reg signed [15:0] diff_p1_r1;
reg signed [15:0] diff_p2_r1;
reg signed [15:0] diff_p3_r1;
reg signed [15:0] diff_p4_r1;
reg signed [15:0] diff_p5_r1;
reg signed [15:0] diff_p6_r1;
reg signed [15:0] diff_p7_r1;

always  @(posedge clk or negedge rstn)begin
if(rstn==1'b0)begin
    diff_p0_r1 <= 0;
    diff_p1_r1 <= 0;
    diff_p2_r1 <= 0;
    diff_p3_r1 <= 0;
    diff_p4_r1 <= 0;
    diff_p5_r1 <= 0;
    diff_p6_r1 <= 0;
    diff_p7_r1 <= 0;

wire [15:0] din_wire [0:3];

assign din_wire[0] = din0;
assign din_wire[1] = din1;
assign din_wire[2] = din2;
assign din_wire[3] = din3;


wire [3:0] vldo_temp;
wire  signed  [15:0]  dinp_r0 [7:0];
genvar i;
generate
    for (i = 0; i < 4; i = i + 1) begin: s2p_inst
        s2p_2 inst_s2p_2 (
            .clk    (clk),
            .rst_n  (rstn),
            .din    (din_wire[i]),
            .en     (vldi),
            .dout0  (dinp_r0[i]),
            .dout1  (dinp_r0[i+4]),
            .vldo   (vldo_temp[i])
        );
    end
endgenerate
assign vldo = vldo_temp[0];

reg  signed [15:0] dinp_r1 [0:7];
integer j;
always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (j = 0; j < 8; j = j + 1) begin
            dinp_r1[j] <= 'h0;
        end
    end 
    else if (en) begin
        for (j = 0; j < 8; j = j + 1) begin
            dinp_r1[j] <= dinp_r0[j];
        end
    end
end

wire signed [15:0] diffp_r0 [0:7];
generate
    for (i = 0; i < 8; i = i + 1) begin: diff_assign
        if (i == 0)
            assign diffp_r0[i] = dinp_r0[i] - dinp_r1[7];
        else
            assign diffp_r0[i] = dinp_r0[i] - dinp_r0[i-1];
    end
endgenerate

assign  dout_p0 = dinp_r1[0];
assign  dout_p1 = dinp_r1[1];
assign  dout_p2 = dinp_r1[2];
assign  dout_p3 = dinp_r1[3];
assign  dout_p4 = dinp_r1[4];
assign  dout_p5 = dinp_r1[5];
assign  dout_p6 = dinp_r1[6];
assign  dout_p7 = dinp_r1[7];

reg  signed [15:0] diffp_r1 [0:7];
always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (j = 0; j < 8; j = j + 1) begin
            diffp_r1[j] <= 0;
        end
    end
    else if (en) begin
        for (j = 0; j < 8; j = j + 1) begin
            diffp_r1[j] <= diffp_r0[j];
        end
    end
end

assign diff_p0 = diffp_r1[0];
assign diff_p1 = diffp_r1[1];
assign diff_p2 = diffp_r1[2];
assign diff_p3 = diffp_r1[3];
assign diff_p4 = diffp_r1[4];
assign diff_p5 = diffp_r1[5];
assign diff_p6 = diffp_r1[6];
assign diff_p7 = diffp_r1[7];

endmodule