module diff(
		 	clk,
		 	rstn,
		 	din,
			dout
);


input rstn;
input clk;
input  signed [15:0] din;

output signed [15:0] dout;


reg	[15:0]  din_r;
reg	[15:0]  din_r1;
reg	[15:0]  out_r;

always@(posedge clk or negedge rstn)
		if(!rstn)
			 begin
				din_r	<=	16'd0;
				din_r1	<=	16'd0;
				
				out_r	<=	16'd0;
			 end 
		else
			 begin
				din_r	<=	din;
				din_r1	<=	din_r;
				
				out_r   <=	din_r - din_r1;
			 end 
assign	dout = out_r;

endmodule