add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/awg}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/clk}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/comm}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/dac_regfile}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/debug}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/define}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/dem}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/modem}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/nco}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/perips}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/qubitmcu}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/rstgen}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/spi}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/sync}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/system_regfile}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/top}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/z_dsp}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/model}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/rx}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/tx}
add_files -fileset sources_1 -scan_for_includes {D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/spi_master}

add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/io/iopad.v

add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/xil_tdpram.v
add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/dpram_model.v
add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/sram_if.sv
add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/sram_dmux.sv
add_files     D:/Work/Z-noSFQ/EZQ-Z-M-v1.0/rtl/memory/dpram.v

add_files     D:/Work/Z-noSFQ/z_chip_top_sram/spi_tx_rx/spram_model_0.v

set_property file_type SystemVerilog [get_files z_awg_ctrl.v]
#synth_design -include_dirs ../../../EZQ-Z-M-v1.0/rtl/define
#synth_design -include_dirs ../../../EZQ-Z-M-v1.0/rtl/qubitmcu