module TB();

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end

reg		clk;
reg		rstn;
reg		en;
reg	[21:0]	cnt;


initial	begin

		#0;
		rstn	= 1'b0;
		clk =  1'b0;
		en  =	1'b0; 
		#300;
		rstn	=	 1'b1;

end

always #200 clk = ~clk;

wire		clk_div16_0;
wire		clk_div16_1;
wire		clk_div16_2;
wire		clk_div16_3;
wire		clk_div16_4;
wire		clk_div16_5;
wire		clk_div16_6;
wire		clk_div16_7;
wire		clk_div16_8;
wire		clk_div16_9;
wire		clk_div16_a;
wire		clk_div16_b;
wire		clk_div16_c;
wire		clk_div16_d;
wire		clk_div16_e;
wire		clk_div16_f;


clk_gen inst_clk_gen(
			                .rstn			(rstn				),
			                .clk			(clk				),
			                .clk_div16_0		(clk_div16_0			),
			                .clk_div16_1		(clk_div16_1			),
			                .clk_div16_2		(clk_div16_2			),
			                .clk_div16_3		(clk_div16_3			),
			                .clk_div16_4		(clk_div16_4			),
			                .clk_div16_5		(clk_div16_5			),
			                .clk_div16_6		(clk_div16_6			),
			                .clk_div16_7		(clk_div16_7			),
			                .clk_div16_8		(clk_div16_8			),
			                .clk_div16_9		(clk_div16_9			),
			                .clk_div16_a		(clk_div16_a			),
			                .clk_div16_b		(clk_div16_b			),
			                .clk_div16_c		(clk_div16_c			),
			                .clk_div16_d		(clk_div16_d			),
			                .clk_div16_e		(clk_div16_e			),
			                .clk_div16_f            (clk_div16_f                    ),
                                        .clk_h                  (clk_h                          ),
                                        .clk_l                  (clk_l                          )
		);

always@(posedge clk_div16_f or negedge rstn)
		if(!rstn)
			cnt	<=	22'd0;
		else
			cnt	<=	cnt + 22'd1;


initial	begin
	wait(cnt[17]==1'b1)
			$finish(0);
end
always@(posedge clk_div16_f or negedge rstn) 
begin
		if(cnt >= 2047 ) 
			   begin
				en    <= 	1'b1;
			    end
		else
			    begin
				en    <= 	1'b0;
			     end
end


reg	[47:0]		fcw;

initial	begin
		fcw	=	48'h0840_0000_0000;
end

wire   [15:0]     cos;
wire   [15:0]     sin;


NCO	inst_nco_0(
                 		.clk				(clk_div16_f  		),
                 		.rstn				(rstn		),
                 		.phase_manual_clr		(1'b0		),
                 		.phase_auto_clr			(1'b0		),
                 		.fcw				(fcw		),
                 		.pha				(16'd0		),
                 		.cos	                        (cos            ),
                 		.sin	                        (sin            )
                	);


wire	[15:0]	dout_p0;
wire	[15:0]	dout_p1;
wire	[15:0]	dout_p2;
wire	[15:0]	dout_p3;

MeanIntp4		inst_MeanIntp4
		       (
				.clk				(clk_div16_f	        ),
				.rstn				(rstn			),
				.en				(en			),
                                .din	                	(cos & {16{en}}         ),           
				.dout4_0			(dout_p0                ),
				.dout4_1			(dout_p1                ),
				.dout4_2			(dout_p2                ),
				.dout4_3			(dout_p3                )
		        );

reg	[15:0]	cs_wave;

always@(posedge clk_div16_e)	cs_wave	 	= dout_p0;
always@(posedge clk_div16_a)	cs_wave	 	= dout_p1;
always@(posedge clk_div16_6)	cs_wave	 	= dout_p2;
always@(posedge clk_div16_2)	cs_wave	 	= dout_p3;

endmodule