//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    Z_dsp.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.3         2024-11-09      thfu            to fit the addition of IP core
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	z_dsp	 	
(
input	 		clk,
input	 		rstn,
input	 		en, 		//enable
input  [1:0] 		dac_mode_sel, 	//2'b00:NRZ mode;2'b01:Double data mode;
                                        //2'b10:Double Double data mode;2'b11:reserve;
input  		 	tc_bypass, 	
input  [1:0]	 	intp_mode, 	//2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
input		        vldi,
input  signed [15:0]	din_re,	
input  signed [15:0]	din_im,	
input  signed [31:0]	a0_re, 		//a0's real part
input  signed [31:0]	a0_im,		//a0's image part
input  signed [31:0]	b0_re,
input  signed [31:0]	b0_im,
input  signed [31:0]	a1_re,
input  signed [31:0]	a1_im,
input  signed [31:0]	b1_re,
input  signed [31:0]	b1_im,
input  signed [31:0]	a2_re,
input  signed [31:0]	a2_im,
input  signed [31:0]	b2_re,
input  signed [31:0]	b2_im,
input  signed [31:0]	a3_re,
input  signed [31:0]	a3_im,
input  signed [31:0]	b3_re,
input  signed [31:0]	b3_im,
input  signed [31:0]	a4_re,
input  signed [31:0]	a4_im,
input  signed [31:0]	b4_re,
input  signed [31:0]	b4_im,
input  signed [31:0]	a5_re,
input  signed [31:0]	a5_im,
input  signed [31:0]	b5_re,
input  signed [31:0]	b5_im,
output signed [15:0]	dout0,
output signed [15:0]	dout1,	
output signed [15:0]	dout2,	
output signed [15:0]	dout3,		
output		        vldo,
output 			saturation_0,
output 			saturation_1,
output 			saturation_2,
output 			saturation_3,
output 			saturation_4,
output 			saturation_5
		 	);		

endmodule