module TB();

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end

reg             clk;
reg             rstn;
reg             en;
reg     [21:0]  cnt;


initial begin

                #0;
                rstn    = 1'b0;
                clk =  1'b0;
                en  =   1'b0; 
                #300;
                rstn    =        1'b1;

end

always #200 clk = ~clk;

wire            clk_div16_0;
wire            clk_div16_1;
wire            clk_div16_2;
wire            clk_div16_3;
wire            clk_div16_4;
wire            clk_div16_5;
wire            clk_div16_6;
wire            clk_div16_7;
wire            clk_div16_8;
wire            clk_div16_9;
wire            clk_div16_a;
wire            clk_div16_b;
wire            clk_div16_c;
wire            clk_div16_d;
wire            clk_div16_e;
wire            clk_div16_f;


clk_gen inst_clk_gen(
                                        .rstn                   (rstn                           ),
                                        .clk                    (clk                            ),
                                        .clk_div16_0            (clk_div16_0                    ),
                                        .clk_div16_1            (clk_div16_1                    ),
                                        .clk_div16_2            (clk_div16_2                    ),
                                        .clk_div16_3            (clk_div16_3                    ),
                                        .clk_div16_4            (clk_div16_4                    ),
                                        .clk_div16_5            (clk_div16_5                    ),
                                        .clk_div16_6            (clk_div16_6                    ),
                                        .clk_div16_7            (clk_div16_7                    ),
                                        .clk_div16_8            (clk_div16_8                    ),
                                        .clk_div16_9            (clk_div16_9                    ),
                                        .clk_div16_a            (clk_div16_a                    ),
                                        .clk_div16_b            (clk_div16_b                    ),
                                        .clk_div16_c            (clk_div16_c                    ),
                                        .clk_div16_d            (clk_div16_d                    ),
                                        .clk_div16_e            (clk_div16_e                    ),
                                        .clk_div16_f            (clk_div16_f                    ),
                            .clk_h                  (clk_h                          ),
                            .clk_l                  (clk_l                          )
                );

always@(posedge clk_div16_f or negedge rstn)
                if(!rstn)
                        cnt     <=      22'd0;
                else
                        cnt     <=      cnt + 22'd1;


initial begin
        wait(cnt[17]==1'b1)
                        $finish(0);
end
always@(posedge clk_div16_f or negedge rstn) 
begin
                if(cnt >= 2047 ) 
                           begin
                                en    <=        1'b1;
                            end
                else
                            begin
                                en    <=        1'b0;
                             end
end


reg     [47:0]          fcw;

initial begin
                fcw     =       48'h0840_0000_0000;
end

wire   [15:0]     cos;
wire   [15:0]     sin;


NCO     inst_nco_0(
                                .clk                            (clk_div16_f            ),
                                .rstn                           (rstn           ),
                                .phase_manual_clr               (1'b0           ),
                                .phase_auto_clr                 (1'b0           ),
                                .fcw                            (fcw            ),
                                .pha                            (16'd0          ),
                                .cos                            (cos            ),
                                .sin                            (sin            )
                        );


wire    [15:0]  dout_p0;
wire    [15:0]  dout_p1;
wire    [15:0]  dout_p2;
wire    [15:0]  dout_p3;
wire    [15:0]  dout_p4;
wire    [15:0]  dout_p5;
wire    [15:0]  dout_p6;
wire    [15:0]  dout_p7;


wire    [1:0]  intp_mode;
assign intp_mode = 2'b11;

MeanIntp_8              inst_MeanIntp8
                       (
                        .clk                        (clk_div16_f            ),
                        .rstn                       (rstn                   ),
                        .en                         (en                     ),
                        .intp_mode                  (intp_mode              ),
                        .din                        (cos & {16{en}}         ),           
                        .dout_0                     (dout_p0                ),
                        .dout_1                     (dout_p1                ),
                        .dout_2                     (dout_p2                ),
                        .dout_3                     (dout_p3                ),
                        .dout_4                     (dout_p4                ),
                        .dout_5                     (dout_p5                ),
                        .dout_6                     (dout_p6                ),
                        .dout_7                     (dout_p7                )

            );
integer  signed In_fid;
integer    X8_fid;

initial  begin
    #0

    In_fid  =  $fopen("./in_intp8.dat");
    X8_fid  =  $fopen("./out_intp8.dat");

end

always@(posedge clk_div16_f)
    if(cnt >= 90)
        $fwrite(In_fid,"%d\n",{{{~cos[15]}},cos[14:0]});

reg     [15:0]  cs_wave;

always@(*)
  fork
//              begin
                        @(posedge clk_div16_e)  cs_wave         = dout_p0;
                        @(posedge clk_div16_c)  cs_wave         = dout_p1;
                        @(posedge clk_div16_a)  cs_wave         = dout_p2;
                        @(posedge clk_div16_8)  cs_wave         = dout_p3;
                        @(posedge clk_div16_6)  cs_wave         = dout_p4;
                        @(posedge clk_div16_4)  cs_wave         = dout_p5;
                        @(posedge clk_div16_2)  cs_wave         = dout_p6;
                        @(posedge clk_div16_0)  cs_wave         = dout_p7;

//        end
  join

always@(*)
    fork

                        @(posedge clk_div16_e)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p0[15]}},dout_p0[14:0]});
                        @(posedge clk_div16_c)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p1[15]}},dout_p1[14:0]});
                        @(posedge clk_div16_a)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p2[15]}},dout_p2[14:0]});
                        @(posedge clk_div16_8)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p3[15]}},dout_p3[14:0]});
                        @(posedge clk_div16_6)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p4[15]}},dout_p4[14:0]});
                        @(posedge clk_div16_4)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p5[15]}},dout_p5[14:0]});
                        @(posedge clk_div16_2)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p6[15]}},dout_p6[14:0]});
                        @(posedge clk_div16_0)
                          if(cnt >= 90)
                                $fwrite(X8_fid,"%d\n",{{{~dout_p7[15]}},dout_p7[14:0]});
    join

endmodule