module	PIPE3_ADD_48BIT(
	clk,
	rstn,
	in,
	clr,
	ptw,
	s1,
	s2,
	s3,
	out
);

//---

  input			clk;
  input			rstn;
  input		[47:0]	in;
  input			clr;
  input		[15:0]	ptw;

  input		[15:0]	s1;
  input		[15:0]	s2;
  input		[15:0]	s3;
  output	[18:0]	out;


//----------------------------------------------------------------------------------------------------

 reg	[47:0]	acc;
   always@(posedge clk or negedge rstn)
      if(!rstn)
		acc<=48'h0;
      else if(clr)
	      	acc<=48'h0;
      else
	      	acc<={s1,s2,s3}+in;
//---

wire[18:0]	pha_w;
assign          pha_w=acc[47:29];
reg[18:0]	pha_r;
always@(posedge clk)
			pha_r<=pha_w+{ptw,3'b0};


 assign	out=pha_r;
//END
endmodule