module z_dsp ( input rstn ,input clk ,input en //,input tc_bypass ,input [ 5:0] vldi_coef ,input vldi_data //,input [1:0] intp_mode //,input [1:0] dac_mode_sel ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31:0] a0_re ,input signed [31:0] b0_re ,input signed [31:0] a1_re ,input signed [31:0] b1_re ,input signed [31:0] a2_re ,input signed [31:0] b2_re ,input signed [31:0] a3_re ,input signed [31:0] b3_re ,input signed [31:0] a4_re ,input signed [31:0] b4_re ,input signed [31:0] a5_re ,input signed [31:0] b5_re ,output signed [15:0] dout0 ,output signed [15:0] dout1 ,output signed [15:0] dout2 ,output signed [15:0] dout3 ,output vldo ); wire signed [15:0] IIR_out; wire signed [31:0] ao_re [5:0]; wire signed [31:0] ab_re [5:0]; wire signed [31:0] abb_re [5:0]; wire signed [31:0] ab_pow3_re [5:0]; wire signed [31:0] ab_pow4_re [5:0]; wire signed [31:0] ab_pow5_re [5:0]; wire signed [31:0] ab_pow6_re [5:0]; wire signed [31:0] ab_pow7_re [5:0]; wire signed [31:0] bo_re [5:0]; wire signed [31:0] b_pow8_re [5:0]; CoefGen inst_CoefGen( .clk (clk ), .rstn (rstn ), .vldi (vldi_coef ), .a0_re (a0_re ), .b0_re (b0_re ), .a1_re (a1_re ), .b1_re (b1_re ), .a2_re (a2_re ), .b2_re (b2_re ), .a3_re (a3_re ), .b3_re (b3_re ), .a4_re (a4_re ), .b4_re (b4_re ), .a5_re (a5_re ), .b5_re (b5_re ), .a_re0 (ao_re[0] ), .b_re0 (bo_re[0] ), .ab_re0 (ab_re[0] ), .abb_re0 (abb_re[0] ), .ab_pow3_re0 (ab_pow3_re[0]), .ab_pow4_re0 (ab_pow4_re[0]), .ab_pow5_re0 (ab_pow5_re[0]), .ab_pow6_re0 (ab_pow6_re[0]), .ab_pow7_re0 (ab_pow7_re[0]), .b_pow8_re0 (b_pow8_re[0] ), .a_re1 (ao_re[1] ), .b_re1 (bo_re[1] ), .ab_re1 (ab_re[1] ), .abb_re1 (abb_re[1] ), .ab_pow3_re1 (ab_pow3_re[1]), .ab_pow4_re1 (ab_pow4_re[1]), .ab_pow5_re1 (ab_pow5_re[1]), .ab_pow6_re1 (ab_pow6_re[1]), .ab_pow7_re1 (ab_pow7_re[1]), .b_pow8_re1 (b_pow8_re[1] ), .a_re2 (ao_re[2] ), .b_re2 (bo_re[2] ), .ab_re2 (ab_re[2] ), .abb_re2 (abb_re[2] ), .ab_pow3_re2 (ab_pow3_re[2]), .ab_pow4_re2 (ab_pow4_re[2]), .ab_pow5_re2 (ab_pow5_re[2]), .ab_pow6_re2 (ab_pow6_re[2]), .ab_pow7_re2 (ab_pow7_re[2]), .b_pow8_re2 (b_pow8_re[2] ), .a_re3 (ao_re[3] ), .b_re3 (bo_re[3] ), .ab_re3 (ab_re[3] ), .abb_re3 (abb_re[3] ), .ab_pow3_re3 (ab_pow3_re[3]), .ab_pow4_re3 (ab_pow4_re[3]), .ab_pow5_re3 (ab_pow5_re[3]), .ab_pow6_re3 (ab_pow6_re[3]), .ab_pow7_re3 (ab_pow7_re[3]), .b_pow8_re3 (b_pow8_re[3] ), .a_re4 (ao_re[4] ), .b_re4 (bo_re[4] ), .ab_re4 (ab_re[4] ), .abb_re4 (abb_re[4] ), .ab_pow3_re4 (ab_pow3_re[4]), .ab_pow4_re4 (ab_pow4_re[4]), .ab_pow5_re4 (ab_pow5_re[4]), .ab_pow6_re4 (ab_pow6_re[4]), .ab_pow7_re4 (ab_pow7_re[4]), .b_pow8_re4 (b_pow8_re[4] ), .a_re5 (ao_re[5] ), .b_re5 (bo_re[5] ), .ab_re5 (ab_re[5] ), .abb_re5 (abb_re[5] ), .ab_pow3_re5 (ab_pow3_re[5]), .ab_pow4_re5 (ab_pow4_re[5]), .ab_pow5_re5 (ab_pow5_re[5]), .ab_pow6_re5 (ab_pow6_re[5]), .ab_pow7_re5 (ab_pow7_re[5]), .b_pow8_re5 (b_pow8_re[5] ) ); wire signed [15:0] dout_0; wire signed [15:0] dout_1; wire signed [15:0] dout_2; wire signed [15:0] dout_3; wire signed [15:0] dout_4; wire signed [15:0] dout_5; wire signed [15:0] dout_6; wire signed [15:0] dout_7; wire vldo_TC; TailCorr_top inst_TailCorr_top ( .clk (clk ), .en (en ), .rstn (rstn ), .vldi (vldi_data ), // .dac_mode_sel (dac_mode_sel ), // .intp_mode (intp_mode ), .din0 (din0 ), .din1 (din1 ), .din2 (din2 ), .din3 (din3 ), .a_re0 (ao_re[0] ), .b_re0 (bo_re[0] ), .ab_re0 (ab_re[0] ), .abb_re0 (abb_re[0] ), .ab_pow3_re0 (ab_pow3_re[0]), .ab_pow4_re0 (ab_pow4_re[0]), .ab_pow5_re0 (ab_pow5_re[0]), .ab_pow6_re0 (ab_pow6_re[0]), .ab_pow7_re0 (ab_pow7_re[0]), .b_pow8_re0 (b_pow8_re[0] ), .a_re1 (ao_re[1] ), .b_re1 (bo_re[1] ), .ab_re1 (ab_re[1] ), .abb_re1 (abb_re[1] ), .ab_pow3_re1 (ab_pow3_re[1]), .ab_pow4_re1 (ab_pow4_re[1]), .ab_pow5_re1 (ab_pow5_re[1]), .ab_pow6_re1 (ab_pow6_re[1]), .ab_pow7_re1 (ab_pow7_re[1]), .b_pow8_re1 (b_pow8_re[1] ), .a_re2 (ao_re[2] ), .b_re2 (bo_re[2] ), .ab_re2 (ab_re[2] ), .abb_re2 (abb_re[2] ), .ab_pow3_re2 (ab_pow3_re[2]), .ab_pow4_re2 (ab_pow4_re[2]), .ab_pow5_re2 (ab_pow5_re[2]), .ab_pow6_re2 (ab_pow6_re[2]), .ab_pow7_re2 (ab_pow7_re[2]), .b_pow8_re2 (b_pow8_re[2] ), .a_re3 (ao_re[3] ), .b_re3 (bo_re[3] ), .ab_re3 (ab_re[3] ), .abb_re3 (abb_re[3] ), .ab_pow3_re3 (ab_pow3_re[3]), .ab_pow4_re3 (ab_pow4_re[3]), .ab_pow5_re3 (ab_pow5_re[3]), .ab_pow6_re3 (ab_pow6_re[3]), .ab_pow7_re3 (ab_pow7_re[3]), .b_pow8_re3 (b_pow8_re[3] ), .a_re4 (ao_re[4] ), .b_re4 (bo_re[4] ), .ab_re4 (ab_re[4] ), .abb_re4 (abb_re[4] ), .ab_pow3_re4 (ab_pow3_re[4]), .ab_pow4_re4 (ab_pow4_re[4]), .ab_pow5_re4 (ab_pow5_re[4]), .ab_pow6_re4 (ab_pow6_re[4]), .ab_pow7_re4 (ab_pow7_re[4]), .b_pow8_re4 (b_pow8_re[4] ), .a_re5 (ao_re[5] ), .b_re5 (bo_re[5] ), .ab_re5 (ab_re[5] ), .abb_re5 (abb_re[5] ), .ab_pow3_re5 (ab_pow3_re[5]), .ab_pow4_re5 (ab_pow4_re[5]), .ab_pow5_re5 (ab_pow5_re[5]), .ab_pow6_re5 (ab_pow6_re[5]), .ab_pow7_re5 (ab_pow7_re[5]), .b_pow8_re5 (b_pow8_re[5] ), .dout_p0 (dout_0 ), .dout_p1 (dout_1 ), .dout_p2 (dout_2 ), .dout_p3 (dout_3 ), .dout_p4 (dout_4 ), .dout_p5 (dout_5 ), .dout_p6 (dout_6 ), .dout_p7 (dout_7 ), .vldo (vldo_TC ) ); //assign vldo = vldo_TC; rate_adapter inst_rate_adapter( .rstn (rstn ), .clk (clk ), .en (en ), .vldi (vldo_TC ), .din0 (dout_0 ), .din1 (dout_1 ), .din2 (dout_2 ), .din3 (dout_3 ), .din4 (dout_4 ), .din5 (dout_5 ), .din6 (dout_6 ), .din7 (dout_7 ), .dout0 (dout0 ), .dout1 (dout1 ), .dout2 (dout2 ), .dout3 (dout3 ), .vldo (vldo ) ); endmodule