//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : IIR_Filter.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.4 2024-05-28 thfu //2024-05-28 10:22:49 //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module CoefGen #( parameter data_in_width = 32 ,parameter coef_width = 32 ,parameter frac_data_out_width = 20//X for in,5 ,parameter frac_coef_width = 31//division ) ( input rstn ,input clk ,input [5:0] vldi ,input signed [coef_width-1 :0] a_re [5:0] ,input signed [coef_width-1 :0] a_im [5:0] ,input signed [coef_width-1 :0] b_re [5:0] ,input signed [coef_width-1 :0] b_im [5:0] ,output reg signed [coef_width-1 :0] ao_re [5:0] ,output reg signed [coef_width-1 :0] ao_im [5:0] ,output reg signed [coef_width-1 :0] ab_re [5:0] ,output reg signed [coef_width-1 :0] ab_im [5:0] ,output reg signed [coef_width-1 :0] abb_re [5:0] ,output reg signed [coef_width-1 :0] abb_im [5:0] ,output reg signed [coef_width-1 :0] ab_pow3_re [5:0] ,output reg signed [coef_width-1 :0] ab_pow3_im [5:0] ,output reg signed [coef_width-1 :0] ab_pow4_re [5:0] ,output reg signed [coef_width-1 :0] ab_pow4_im [5:0] ,output reg signed [coef_width-1 :0] ab_pow5_re [5:0] ,output reg signed [coef_width-1 :0] ab_pow5_im [5:0] ,output reg signed [coef_width-1 :0] ab_pow6_re [5:0] ,output reg signed [coef_width-1 :0] ab_pow6_im [5:0] ,output reg signed [coef_width-1 :0] ab_pow7_re [5:0] ,output reg signed [coef_width-1 :0] ab_pow7_im [5:0] ,output reg signed [coef_width-1 :0] b_pow8_re [5:0] ,output reg signed [coef_width-1 :0] b_pow8_im [5:0] ); reg vldi_or_r1; wire vldi_or = | vldi; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldi_or_r1 <= 'h0; end else begin vldi_or_r1 <= vldi_or; end end reg signed [data_in_width-1:0] a_re_r1; reg signed [data_in_width-1:0] a_im_r1; reg signed [data_in_width-1:0] b_re_r1; reg signed [data_in_width-1:0] b_im_r1; always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin a_re_r1 <= 'h0; a_im_r1 <= 'h0; b_re_r1 <= 'h0; b_im_r1 <= 'h0; end else if(|vldi) begin case(1'b1) vldi[0]: begin a_re_r1 <= a_re[0]; a_im_r1 <= a_im[0]; b_re_r1 <= b_re[0]; b_im_r1 <= b_im[0]; end vldi[1]: begin a_re_r1 <= a_re[1]; a_im_r1 <= a_im[1]; b_re_r1 <= b_re[1]; b_im_r1 <= b_im[1]; end vldi[2]: begin a_re_r1 <= a_re[2]; a_im_r1 <= a_im[2]; b_re_r1 <= b_re[2]; b_im_r1 <= b_im[2]; end vldi[3]: begin a_re_r1 <= a_re[3]; a_im_r1 <= a_im[3]; b_re_r1 <= b_re[3]; b_im_r1 <= b_im[3]; end vldi[4]: begin a_re_r1 <= a_re[4]; a_im_r1 <= a_im[4]; b_re_r1 <= b_re[4]; b_im_r1 <= b_im[4]; end vldi[5]: begin a_re_r1 <= a_re[5]; a_im_r1 <= a_im[5]; b_re_r1 <= b_re[5]; b_im_r1 <= b_im[5]; end // default: begin // a_re_r1 <= a_re[0]; // a_im_r1 <= a_im[0]; // b_re_r1 <= b_re[0]; // b_im_r1 <= b_im[0]; // end endcase end end reg en; reg en_r1; reg [3:0] cnt0; wire add_cnt0; wire end_cnt0; always @(posedge clk or negedge rstn)begin if(!rstn)begin cnt0 <= 0; end else if(add_cnt0)begin if(end_cnt0) cnt0 <= 0; else cnt0 <= cnt0 + 1; end end assign add_cnt0 = en; assign end_cnt0 = add_cnt0 && cnt0== 8-1; wire en_l; wire en_h; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin en <= 0; end else if(en_h)begin en <= 1; end else if(en_l)begin en <= 0; end end assign en_h = vldi_or == 1 && vldi_or_r1 == 0 && cnt0 == 0; assign en_l = end_cnt0; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin en_r1 <= 'h0; end else begin en_r1 <= en; end end reg signed [data_in_width-1:0] bin_re; reg signed [data_in_width-1:0] bin_im; wire signed [data_in_width-1:0] bout_re; wire signed [data_in_width-1:0] bout_im; always @(*)begin if(en_r1) begin bin_re <= bout_re; bin_im <= bout_im; end else begin bin_re <= 32'd2147483647; bin_im <= 0; end end mult_C #( .A_width(data_in_width) ,.B_width(data_in_width) ,.C_width(coef_width) ,.D_width(coef_width) ,.frac_coef_width(frac_coef_width) ) inst_c1 ( .clk (clk ), .rstn (rstn ), .en (en ), .a (bin_re ), .b (bin_im ), .c (b_re_r1 ), .d (b_im_r1 ), .Re (bout_re ), .Im (bout_im ) ); wire signed [data_in_width-1:0] abo_re; wire signed [data_in_width-1:0] abo_im; mult_C #( .A_width(data_in_width) ,.B_width(data_in_width) ,.C_width(coef_width) ,.D_width(coef_width) ,.frac_coef_width(frac_coef_width) ) inst_c2 ( .clk (clk ), .rstn (rstn ), .en (en ), .a (bin_re ), .b (bin_im ), .c (a_re_r1 ), .d (a_im_r1 ), .Re (abo_re ), .Im (abo_im ) ); reg signed [coef_width-1 :0] ao_re_r1 ; reg signed [coef_width-1 :0] ao_im_r1 ; reg signed [coef_width-1 :0] ab_re_r1 ; reg signed [coef_width-1 :0] ab_im_r1 ; reg signed [coef_width-1 :0] abb_re_r1 ; reg signed [coef_width-1 :0] abb_im_r1 ; reg signed [coef_width-1 :0] ab_pow3_re_r1 ; reg signed [coef_width-1 :0] ab_pow3_im_r1 ; reg signed [coef_width-1 :0] ab_pow4_re_r1 ; reg signed [coef_width-1 :0] ab_pow4_im_r1 ; reg signed [coef_width-1 :0] ab_pow5_re_r1 ; reg signed [coef_width-1 :0] ab_pow5_im_r1 ; reg signed [coef_width-1 :0] ab_pow6_re_r1 ; reg signed [coef_width-1 :0] ab_pow6_im_r1 ; reg signed [coef_width-1 :0] ab_pow7_re_r1 ; reg signed [coef_width-1 :0] ab_pow7_im_r1 ; reg signed [coef_width-1 :0] b_pow8_re_r1 ; reg signed [coef_width-1 :0] b_pow8_im_r1 ; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin ao_re_r1 <= 0; ao_im_r1 <= 0; ab_re_r1 <= 0; ab_im_r1 <= 0; abb_re_r1 <= 0; abb_im_r1 <= 0; ab_pow3_re_r1 <= 0; ab_pow3_im_r1 <= 0; ab_pow4_re_r1 <= 0; ab_pow4_im_r1 <= 0; ab_pow5_re_r1 <= 0; ab_pow5_im_r1 <= 0; ab_pow6_re_r1 <= 0; ab_pow6_im_r1 <= 0; ab_pow7_re_r1 <= 0; ab_pow7_im_r1 <= 0; b_pow8_re_r1 <= 0; b_pow8_im_r1 <= 0; end else if(add_cnt0 && cnt0 == 1 && en_r1)begin ao_re_r1 <= abo_re; ao_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 2 && en_r1)begin ab_re_r1 <= abo_re; ab_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 3 && en_r1)begin abb_re_r1 <= abo_re; abb_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 4 && en_r1)begin ab_pow3_re_r1 <= abo_re; ab_pow3_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 5 && en_r1)begin ab_pow4_re_r1 <= abo_re; ab_pow4_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 6 && en_r1)begin ab_pow5_re_r1 <= abo_re; ab_pow5_im_r1 <= abo_im; end else if(add_cnt0 && cnt0 == 7 && en_r1)begin ab_pow6_re_r1 <= abo_re; ab_pow6_im_r1 <= abo_im; end else if(cnt0 == 0 && en_r1)begin ab_pow7_re_r1 <= abo_re; ab_pow7_im_r1 <= abo_im; b_pow8_re_r1 <= bin_re; b_pow8_im_r1 <= bin_im; end // else begin // end end reg [5:0] vldi_r10; syncer #(6, 10) sync_vldo_syncer (clk, rstn, vldi, vldi_r10); always @(posedge clk or negedge rstn) begin if(rstn == 1'b0) begin ao_re[0] <= 0; ao_im[0] <= 0; ab_re[0] <= 0; ab_im[0] <= 0; abb_re[0] <= 0; abb_im[0] <= 0; ab_pow3_re[0] <= 0; ab_pow3_im[0] <= 0; ab_pow4_re[0] <= 0; ab_pow4_im[0] <= 0; ab_pow5_re[0] <= 0; ab_pow5_im[0] <= 0; ab_pow6_re[0] <= 0; ab_pow6_im[0] <= 0; ab_pow7_re[0] <= 0; ab_pow7_im[0] <= 0; b_pow8_re[0] <= 0; b_pow8_im[0] <= 0; ao_re[1] <= 0; ao_im[1] <= 0; ab_re[1] <= 0; ab_im[1] <= 0; abb_re[1] <= 0; abb_im[1] <= 0; ab_pow3_re[1] <= 0; ab_pow3_im[1] <= 0; ab_pow4_re[1] <= 0; ab_pow4_im[1] <= 0; ab_pow5_re[1] <= 0; ab_pow5_im[1] <= 0; ab_pow6_re[1] <= 0; ab_pow6_im[1] <= 0; ab_pow7_re[1] <= 0; ab_pow7_im[1] <= 0; b_pow8_re[1] <= 0; b_pow8_im[1] <= 0; ao_re[2] <= 0; ao_im[2] <= 0; ab_re[2] <= 0; ab_im[2] <= 0; abb_re[2] <= 0; abb_im[2] <= 0; ab_pow3_re[2] <= 0; ab_pow3_im[2] <= 0; ab_pow4_re[2] <= 0; ab_pow4_im[2] <= 0; ab_pow5_re[2] <= 0; ab_pow5_im[2] <= 0; ab_pow6_re[2] <= 0; ab_pow6_im[2] <= 0; ab_pow7_re[2] <= 0; ab_pow7_im[2] <= 0; b_pow8_re[2] <= 0; b_pow8_im[2] <= 0; ao_re[3] <= 0; ao_im[3] <= 0; ab_re[3] <= 0; ab_im[3] <= 0; abb_re[3] <= 0; abb_im[3] <= 0; ab_pow3_re[3] <= 0; ab_pow3_im[3] <= 0; ab_pow4_re[3] <= 0; ab_pow4_im[3] <= 0; ab_pow5_re[3] <= 0; ab_pow5_im[3] <= 0; ab_pow6_re[3] <= 0; ab_pow6_im[3] <= 0; ab_pow7_re[3] <= 0; ab_pow7_im[3] <= 0; b_pow8_re[3] <= 0; b_pow8_im[3] <= 0; ao_re[4] <= 0; ao_im[4] <= 0; ab_re[4] <= 0; ab_im[4] <= 0; abb_re[4] <= 0; abb_im[4] <= 0; ab_pow3_re[4] <= 0; ab_pow3_im[4] <= 0; ab_pow4_re[4] <= 0; ab_pow4_im[4] <= 0; ab_pow5_re[4] <= 0; ab_pow5_im[4] <= 0; ab_pow6_re[4] <= 0; ab_pow6_im[4] <= 0; ab_pow7_re[4] <= 0; ab_pow7_im[4] <= 0; b_pow8_re[4] <= 0; b_pow8_im[4] <= 0; ao_re[5] <= 0; ao_im[5] <= 0; ab_re[5] <= 0; ab_im[5] <= 0; abb_re[5] <= 0; abb_im[5] <= 0; ab_pow3_re[5] <= 0; ab_pow3_im[5] <= 0; ab_pow4_re[5] <= 0; ab_pow4_im[5] <= 0; ab_pow5_re[5] <= 0; ab_pow5_im[5] <= 0; ab_pow6_re[5] <= 0; ab_pow6_im[5] <= 0; ab_pow7_re[5] <= 0; ab_pow7_im[5] <= 0; b_pow8_re[5] <= 0; b_pow8_im[5] <= 0; end else if(|vldi_r10) begin case(1'b1) vldi_r10[0]: begin ao_re[0] <= ao_re_r1 ; ao_im[0] <= ao_im_r1 ; ab_re[0] <= ab_re_r1 ; ab_im[0] <= ab_im_r1 ; abb_re[0] <= abb_re_r1 ; abb_im[0] <= abb_im_r1 ; ab_pow3_re[0] <= ab_pow3_re_r1; ab_pow3_im[0] <= ab_pow3_im_r1; ab_pow4_re[0] <= ab_pow4_re_r1; ab_pow4_im[0] <= ab_pow4_im_r1; ab_pow5_re[0] <= ab_pow5_re_r1; ab_pow5_im[0] <= ab_pow5_im_r1; ab_pow6_re[0] <= ab_pow6_re_r1; ab_pow6_im[0] <= ab_pow6_im_r1; ab_pow7_re[0] <= ab_pow7_re_r1; ab_pow7_im[0] <= ab_pow7_im_r1; b_pow8_re[0] <= b_pow8_re_r1 ; b_pow8_im[0] <= b_pow8_im_r1 ; end vldi_r10[1]: begin ao_re[1] <= ao_re_r1 ; ao_im[1] <= ao_im_r1 ; ab_re[1] <= ab_re_r1 ; ab_im[1] <= ab_im_r1 ; abb_re[1] <= abb_re_r1 ; abb_im[1] <= abb_im_r1 ; ab_pow3_re[1] <= ab_pow3_re_r1; ab_pow3_im[1] <= ab_pow3_im_r1; ab_pow4_re[1] <= ab_pow4_re_r1; ab_pow4_im[1] <= ab_pow4_im_r1; ab_pow5_re[1] <= ab_pow5_re_r1; ab_pow5_im[1] <= ab_pow5_im_r1; ab_pow6_re[1] <= ab_pow6_re_r1; ab_pow6_im[1] <= ab_pow6_im_r1; ab_pow7_re[1] <= ab_pow7_re_r1; ab_pow7_im[1] <= ab_pow7_im_r1; b_pow8_re[1] <= b_pow8_re_r1 ; b_pow8_im[1] <= b_pow8_im_r1 ; end vldi_r10[2]: begin ao_re[2] <= ao_re_r1 ; ao_im[2] <= ao_im_r1 ; ab_re[2] <= ab_re_r1 ; ab_im[2] <= ab_im_r1 ; abb_re[2] <= abb_re_r1 ; abb_im[2] <= abb_im_r1 ; ab_pow3_re[2] <= ab_pow3_re_r1; ab_pow3_im[2] <= ab_pow3_im_r1; ab_pow4_re[2] <= ab_pow4_re_r1; ab_pow4_im[2] <= ab_pow4_im_r1; ab_pow5_re[2] <= ab_pow5_re_r1; ab_pow5_im[2] <= ab_pow5_im_r1; ab_pow6_re[2] <= ab_pow6_re_r1; ab_pow6_im[2] <= ab_pow6_im_r1; ab_pow7_re[2] <= ab_pow7_re_r1; ab_pow7_im[2] <= ab_pow7_im_r1; b_pow8_re[2] <= b_pow8_re_r1 ; b_pow8_im[2] <= b_pow8_im_r1 ; end vldi_r10[3]: begin ao_re[3] <= ao_re_r1 ; ao_im[3] <= ao_im_r1 ; ab_re[3] <= ab_re_r1 ; ab_im[3] <= ab_im_r1 ; abb_re[3] <= abb_re_r1 ; abb_im[3] <= abb_im_r1 ; ab_pow3_re[3] <= ab_pow3_re_r1; ab_pow3_im[3] <= ab_pow3_im_r1; ab_pow4_re[3] <= ab_pow4_re_r1; ab_pow4_im[3] <= ab_pow4_im_r1; ab_pow5_re[3] <= ab_pow5_re_r1; ab_pow5_im[3] <= ab_pow5_im_r1; ab_pow6_re[3] <= ab_pow6_re_r1; ab_pow6_im[3] <= ab_pow6_im_r1; ab_pow7_re[3] <= ab_pow7_re_r1; ab_pow7_im[3] <= ab_pow7_im_r1; b_pow8_re[3] <= b_pow8_re_r1 ; b_pow8_im[3] <= b_pow8_im_r1 ; end vldi_r10[4]: begin ao_re[4] <= ao_re_r1 ; ao_im[4] <= ao_im_r1 ; ab_re[4] <= ab_re_r1 ; ab_im[4] <= ab_im_r1 ; abb_re[4] <= abb_re_r1 ; abb_im[4] <= abb_im_r1 ; ab_pow3_re[4] <= ab_pow3_re_r1; ab_pow3_im[4] <= ab_pow3_im_r1; ab_pow4_re[4] <= ab_pow4_re_r1; ab_pow4_im[4] <= ab_pow4_im_r1; ab_pow5_re[4] <= ab_pow5_re_r1; ab_pow5_im[4] <= ab_pow5_im_r1; ab_pow6_re[4] <= ab_pow6_re_r1; ab_pow6_im[4] <= ab_pow6_im_r1; ab_pow7_re[4] <= ab_pow7_re_r1; ab_pow7_im[4] <= ab_pow7_im_r1; b_pow8_re[4] <= b_pow8_re_r1 ; b_pow8_im[4] <= b_pow8_im_r1 ; end vldi_r10[5]: begin ao_re[5] <= ao_re_r1 ; ao_im[5] <= ao_im_r1 ; ab_re[5] <= ab_re_r1 ; ab_im[5] <= ab_im_r1 ; abb_re[5] <= abb_re_r1 ; abb_im[5] <= abb_im_r1 ; ab_pow3_re[5] <= ab_pow3_re_r1; ab_pow3_im[5] <= ab_pow3_im_r1; ab_pow4_re[5] <= ab_pow4_re_r1; ab_pow4_im[5] <= ab_pow4_im_r1; ab_pow5_re[5] <= ab_pow5_re_r1; ab_pow5_im[5] <= ab_pow5_im_r1; ab_pow6_re[5] <= ab_pow6_re_r1; ab_pow6_im[5] <= ab_pow6_im_r1; ab_pow7_re[5] <= ab_pow7_re_r1; ab_pow7_im[5] <= ab_pow7_im_r1; b_pow8_re[5] <= b_pow8_re_r1 ; b_pow8_im[5] <= b_pow8_im_r1 ; end // default: begin // ao_re[0] <= 'h0; // ao_im[0] <= 'h0; // ab_re[0] <= 'h0; // ab_im[0] <= 'h0; // abb_re[0] <= 'h0; // abb_im[0] <= 'h0; // ab_pow3_re[0] <= 'h0; // ab_pow3_im[0] <= 'h0; // ab_pow4_re[0] <= 'h0; // ab_pow4_im[0] <= 'h0; // ab_pow5_re[0] <= 'h0; // ab_pow5_im[0] <= 'h0; // ab_pow6_re[0] <= 'h0; // ab_pow6_im[0] <= 'h0; // ab_pow7_re[0] <= 'h0; // ab_pow7_im[0] <= 'h0; // b_pow8_re[0] <= 'h0; // b_pow8_im[0] <= 'h0; // end endcase end end endmodule