module IIR_top #( parameter data_out_width = 18 ,parameter coef_width = 32 ,parameter a0_width = 32 ,parameter b0_width = 29 ,parameter b0_i_width = 29 ,parameter b0_o_width = 19 ,parameter a1_width = 19 ,parameter b1_width = 19 ,parameter b1_i_width = 19 ,parameter b1_o_width = 19 ,parameter a2_width = 21 ,parameter b2_width = 21 ,parameter b2_i_width = 19 ,parameter b2_o_width = 19 ,parameter a3_width = 21 ,parameter b3_width = 21 ,parameter b3_i_width = 19 ,parameter b3_o_width = 19 ,parameter a4_width = 20 ,parameter b4_width = 20 ,parameter b4_i_width = 19 ,parameter b4_o_width = 18 ,parameter a5_width = 21 ,parameter b5_width = 21 ,parameter b5_i_width = 18 ,parameter b5_o_width = 18 ,parameter a6_width = 21 ,parameter b6_width = 21 ,parameter b6_i_width = 18 ,parameter b6_o_width = 18 ,parameter a7_width = 22 ,parameter b7_width = 22 ,parameter b7_i_width = 18 ,parameter b7_o_width = 18 ) ( input rstn ,input clk ,input en ,input signed [15 :0] IIRin_p0 // x(8n+9) ,input signed [15 :0] IIRin_p1 // x(8n+10) ,input signed [15 :0] IIRin_p2 // x(8n+11) ,input signed [15 :0] IIRin_p3 // x(8n+12) ,input signed [15 :0] IIRin_p4 // x(8n+13) ,input signed [15 :0] IIRin_p5 // x(8n+14) ,input signed [15 :0] IIRin_p6 // x(8n+15) ,input signed [15 :0] IIRin_p7 // x(8n+16) ,input signed [15 :0] IIRin_p0_r2 // x(8n+9) delay 2M -> x(8n- 7) ,input signed [15 :0] IIRin_p1_r4 // x(8n+10) delay 4M -> x(8n-22) ,input signed [15 :0] IIRin_p2_r6 // x(8n+11) delay 6M -> x(8n-37) ,input signed [15 :0] IIRin_p3_r8 // x(8n+12) delay 8M -> x(8n-52) ,input signed [15 :0] IIRin_p4_r10 // x(8n+13) delay 10M -> x(8n-67) ,input signed [15 :0] IIRin_p5_r12 // x(8n+14) delay 12M -> x(8n-82) ,input signed [15 :0] IIRin_p6_r14 // x(8n+15) delay 14M -> x(8n-97) ,input signed [31 :0] a_re ,input signed [31 :0] b_re ,input signed [31 :0] ab_re ,input signed [31 :0] abb_re ,input signed [31 :0] ab_pow3_re ,input signed [31 :0] ab_pow4_re ,input signed [31 :0] ab_pow5_re ,input signed [31 :0] ab_pow6_re ,input signed [31 :0] ab_pow7_re ,input signed [31 :0] b_pow8_re ,output signed [data_out_width-1 :0] IIRout_p0 // y(8n-8) ,output signed [data_out_width-1 :0] IIRout_p1 // y(8n-23) ,output signed [data_out_width-1 :0] IIRout_p2 // y(8n-38) ,output signed [data_out_width-1 :0] IIRout_p3 // y(8n-53) ,output signed [data_out_width-1 :0] IIRout_p4 // y(8n-68) ,output signed [data_out_width-1 :0] IIRout_p5 // y(8n-83) ,output signed [data_out_width-1 :0] IIRout_p6 // y(8n-98) ,output signed [data_out_width-1 :0] IIRout_p7 // y(8n-113) ); wire signed [b0_o_width- 1:0] IIRout_p0_re; wire signed [b1_o_width- 1:0] IIRout_p1_re; wire signed [b2_o_width- 1:0] IIRout_p2_re; wire signed [b3_o_width- 1:0] IIRout_p3_re; wire signed [b4_o_width- 1:0] IIRout_p4_re; wire signed [b5_o_width- 1:0] IIRout_p5_re; wire signed [b6_o_width- 1:0] IIRout_p6_re; wire signed [b7_o_width- 1:0] IIRout_p7_re; IIR_Filter_p8 #( .coef_width (coef_width ), .b_pow8_width (b0_width ), .ab_pow_width (a0_width ), .temp_var_width (b0_i_width ), .data_out_width (b0_o_width ) ) inst_iir_p0 ( .clk (clk ), .rstn (rstn ), .en (en ), .dinp0 (IIRin_p7 ), // x(8n+16) .dinp1 (IIRin_p6 ), // x(8n+15) .dinp2 (IIRin_p5 ), // x(8n+14) .dinp3 (IIRin_p4 ), // x(8n+13) .dinp4 (IIRin_p3 ), // x(8n+12) .dinp5 (IIRin_p2 ), // x(8n+11) .dinp6 (IIRin_p1 ), // x(8n+10) .dinp7 (IIRin_p0 ), // x(8n+9) .a_re (a_re ), .ab_re (ab_re ), .abb_re (abb_re ), .ab_pow3_re (ab_pow3_re ), .ab_pow4_re (ab_pow4_re ), .ab_pow5_re (ab_pow5_re ), .ab_pow6_re (ab_pow6_re ), .ab_pow7_re (ab_pow7_re ), .b_pow8_re (b_pow8_re ), .dout_re (IIRout_p0_re ) // Re(y(8n-8)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a1_width ), .b_width (b1_width ), .cascade_in_width (b1_i_width ), .data_out_width (b1_o_width ) ) inst_iir_p1( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p0_r2 ), // x(8n-7) .dout_r1_re (IIRout_p0_re ), // Re(y(8n-8)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p1_re ) // Re(y(8n-23)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a2_width ), .b_width (b2_width ), .cascade_in_width (b2_i_width ), .data_out_width (b2_o_width ) ) inst_iir_p2 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p1_r4 ), // x(8n-22) .dout_r1_re (IIRout_p1_re ), // Re(y(8n-23)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p2_re ) // Re(y(8n-38)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a3_width ), .b_width (b3_width ), .cascade_in_width (b3_i_width ), .data_out_width (b3_o_width ) ) inst_iir_p3 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p2_r6 ), // x(8n-37) .dout_r1_re (IIRout_p2_re ), // Re(y(8n-38)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p3_re ) // Re(y(8n-53)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a4_width ), .b_width (b4_width ), .cascade_in_width (b4_i_width ), .data_out_width (b4_o_width ) ) inst_iir_p4 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p3_r8 ), // x(8n-52) .dout_r1_re (IIRout_p3_re ), // Re(y(8n-53)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p4_re ) // Re(y(8n-68)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a5_width ), .b_width (b5_width ), .cascade_in_width (b5_i_width ), .data_out_width (b5_o_width ) ) inst_iir_p5 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p4_r10 ), // x(8n-67) .dout_r1_re (IIRout_p4_re ), // Re(y(8n-68)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p5_re ) // Re(y(8n-83)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a6_width ), .b_width (b6_width ), .cascade_in_width (b6_i_width ), .data_out_width (b6_o_width ) ) inst_iir_p6 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p5_r12 ), // x(8n-82) .dout_r1_re (IIRout_p5_re ), // Re(y(8n-83)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p6_re ) // Re(y(8n-98)) ); IIR_Filter_p1 #( .coef_width (coef_width ), .a_width (a7_width ), .b_width (b7_width ), .cascade_in_width (b7_i_width ), .data_out_width (b7_o_width ) ) inst_iir_p7 ( .clk (clk ), .rstn (rstn ), .en (en ), .din_re (IIRin_p6_r14 ), // x(8n-97) .dout_r1_re (IIRout_p6_re ), // Re(y(8n-98)) .a_re (a_re ), .b_re (b_re ), .dout_re (IIRout_p7_re ) // Re(y(8n-113)) ); assign IIRout_p0 = IIRout_p0_re[b0_o_width-1 : b0_o_width-data_out_width]; // y(8n-8) assign IIRout_p1 = IIRout_p1_re[b1_o_width-1 : b1_o_width-data_out_width]; // y(8n-23) assign IIRout_p2 = IIRout_p2_re[b2_o_width-1 : b2_o_width-data_out_width]; // y(8n-38) assign IIRout_p3 = IIRout_p3_re[b3_o_width-1 : b3_o_width-data_out_width]; // y(8n-53) assign IIRout_p4 = IIRout_p4_re[b4_o_width-1 : b4_o_width-data_out_width]; // y(8n-68) assign IIRout_p5 = IIRout_p5_re[b5_o_width-1 : b5_o_width-data_out_width]; // y(8n-83) assign IIRout_p6 = IIRout_p6_re[b6_o_width-1 : b6_o_width-data_out_width]; // y(8n-98) assign IIRout_p7 = IIRout_p7_re[b7_o_width-1 : b7_o_width-data_out_width]; // y(8n-113) endmodule