//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    mult_C.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-28      thfu
//2024-05-28 10:22:18 
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C #(
 parameter    integer    A_width = 8
,parameter    integer    B_width = 8
,parameter    integer    C_width = 8
,parameter    integer    D_width = 8
,parameter    integer    frac_coef_width = 31//division

)

(
            clk,
            rstn,
            en,
            a,
            b,
	    c,
	    d,
	    Re,
	    Im
);

input                                       rstn;
input                                       clk;
input                                       en;
input       signed  [A_width-1:0]           a;
input       signed  [B_width-1:0]           b;
input       signed  [C_width-1:0]           c;
input       signed  [D_width-1:0]           d;

output      signed  [A_width+C_width-frac_coef_width-1:0]  Re;
output      signed  [A_width+D_width-frac_coef_width-1:0]  Im;

wire	    signed	[A_width+C_width-1:0]	ac;
wire	    signed	[B_width+D_width-1:0]	bd;
wire	    signed	[A_width+D_width-1:0]	ad;
wire	    signed	[B_width+C_width-1:0]	bc;



DW02_mult	#(A_width,C_width) inst_c1(	.A		(a		),
						.B		(c		),
						.TC		(1'b1		),
						.PRODUCT	(ac		)
				);

DW02_mult	#(B_width,D_width) inst_c2(	.A		(b		),
						.B		(d		),
						.TC		(1'b1		),
						.PRODUCT	(bd		)
				);

DW02_mult	#(A_width,D_width) inst_c3(	.A		(a		),
						.B		(d		),
						.TC		(1'b1		),
						.PRODUCT	(ad		)
				);
DW02_mult	#(B_width,C_width) inst_c4(	.A		(b		),
						.B		(c		),
						.TC		(1'b1		),
						.PRODUCT	(bc		)
				);
wire         signed  [A_width+C_width:0]     Re_tmp;
wire         signed  [A_width+D_width:0]     Im_tmp;

assign    Re_tmp  =  ac - bd;
assign    Im_tmp  =  ad + bc;

wire         signed  [A_width+C_width:0]     Re_round;
wire         signed  [A_width+D_width:0]     Im_round;

FixRound #(A_width+C_width+1,frac_coef_width) u_round1 (clk, rstn, en, Re_tmp, Re_round);
FixRound #(A_width+C_width+1,frac_coef_width) u_round2 (clk, rstn, en, Im_tmp, Im_round);

assign	Re = Re_round[A_width+D_width-1:frac_coef_width];
assign	Im = Im_round[A_width+D_width-1:frac_coef_width];

endmodule