`timescale 1 ns/1 ns
module TB();
//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    tb_TailCorr_en.v
//  Department            :    HFNL
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//              2025-03-03      thfu
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------


reg    [1 :0]  source_mode;

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
     $fsdbDumpMDA();
//     $srandom(417492050);
     source_mode  =  2'd3;  //1 for rect;2 for random;3 from matlab
end

reg             rstn;

reg     [15:0]  din_rect;
reg     [ 5:0]  vldi_coef;
reg             vldi_data;

parameter CYCLE    = 20;

reg             clk;
initial begin
    clk = 0;
    forever
    #(CYCLE/2)
    clk=~clk;
end


reg signed [31:0] a_re  [5:0];
reg signed [31:0] a_im  [5:0];
reg signed [31:0] b_re  [5:0];
reg signed [31:0] b_im  [5:0];

initial begin
    rstn = 0;
    vldi_data <= 0;
    vldi_coef <= 0;
    din_rect  =      16'd0; 
    repeat(3) @(posedge clk);
        vldi_coef[0] <= 1; 
        rstn = 1;
        a_re[0]     <=      55007237;
        a_im[0]     <=      0;
        b_re[0]     <=      2143083068;
        b_im[0]     <=      0;
    @(posedge clk);
        vldi_coef[0] <= 0; 
        a_re[0]     <=      0;
        a_im[0]     <=      0;
        b_re[0]     <=      0;
        b_im[0]     <=      0;
    repeat(8) @(posedge clk);
        vldi_coef[1] <= 1; 
        rstn = 1;
        a_re[1]     <=      32690030;
        a_im[1]     <=      0;
        b_re[1]     <=      2145807236;
        b_im[1]     <=      0;
    @(posedge clk);
        vldi_coef[1] <= 0; 
        a_re[1]     <=      0;
        a_im[1]     <=      0;
        b_re[1]     <=      0;
        b_im[1]     <=      0;
    repeat(8) @(posedge clk);
        vldi_coef[2] <= 1; 
        rstn = 1;
        a_re[2]     <=      429516;
        a_im[2]     <=      0;
        b_re[2]     <=      2146812530;
        b_im[2]     <=      0;
    @(posedge clk);
        vldi_coef[2] <= 0; 
        a_re[2]     <=      0;
        a_im[2]     <=      0;
        b_re[2]     <=      0;
        b_im[2]     <=      0;
    repeat(108) @(posedge clk);
        vldi_data <= 1; 
//    repeat(10000) @(posedge clk);
//        vldi_data <= 0; 

end

reg     [21:0]  cnt;
always@(posedge clk or negedge rstn)
                if(!rstn)
                        cnt     <=      22'd0;
                else
                        cnt     <=      cnt + 22'd1;

initial 
begin
        wait(cnt[16]==1'b1)
                        $finish(0);
end
                  
reg vldi_data_r1;
always@(posedge clk or negedge rstn)
                if(!rstn)
                        vldi_data_r1        <=      1'b0;
                else 
                    begin
                        vldi_data_r1        <=      vldi_data;
                    end

always@(posedge clk or negedge rstn)
                if(!rstn)
                        din_rect        <=      22'd0;
                else if(vldi_data)
                    begin
                        din_rect        <=      16'd30000;
                    end
                else 
                    begin
                        din_rect        <=      16'd0;
                    end

reg  signed  [15:0]  random_in [0:3];

always @(posedge clk or negedge rstn) begin
    if (!rstn) begin
        for (int i = 0; i < 4; i = i + 1) begin
            random_in[i] <= 16'd0;
        end
    end
    else if (vldi_data) begin
        for (int i = 0; i < 4; i = i + 1) begin
            random_in[i] <= $urandom % 30000;
        end
    end
    else begin
        for (int i = 0; i < 4; i = i + 1) begin
            random_in[i] <= 16'd0;
        end
    end
end

integer file[3:0];
reg [15:0] data[3:0];
integer status[3:0];
reg [15:0] reg_array[3:0];
  
initial begin
    string filenames[0:3] = {"in0_matlab.dat", "in1_matlab.dat", "in2_matlab.dat", "in3_matlab.dat"};    
    for (int i = 0; i < 4; i = i + 1) begin
        file[i] = $fopen(filenames[i], "r");
        if (file[i] == 0) begin
            $display("Failed to open file: %s", filenames[i]);
            $finish;
        end
    end
end

    always @(posedge clk or negedge rstn) begin
        if (!rstn) begin
            for (int i = 0; i < 4; i = i + 1) begin
                    reg_array[i] <= 16'd0;
            end            
        end else  if(vldi_data) begin
            for (int i = 0; i < 4; i = i + 1) begin
                status[i] = $fscanf(file[i], "%d\n", data[i]);
                if (status[i] == 1  ) begin
                    reg_array[i] <= data[i];
                end
                else begin
                    reg_array[i] <= 16'd0;
                    vldi_data <= 0;                    
                end               
            end
        end
    end
reg signed [15:0] iir_in[3:0];

always @(*)
        case(source_mode)
               2'b01 :   begin 
                                 for (int i = 0; i < 4; i = i + 1) begin
                                         iir_in[i] = din_rect;
                                 end            
                          end
               2'b10 :   begin 
                                 for (int i = 0; i < 4; i = i + 1) begin
                                         iir_in[i] = random_in[i];
                                 end            
                          end
               2'b11 :   begin 
                                 for (int i = 0; i < 4; i = i + 1) begin
                                         iir_in[i] = reg_array[i];
                                 end            
                          end
        endcase

wire    [1:0]  intp_mode;
assign intp_mode = 2'b10;

wire    [1:0]  dac_mode_sel;
assign dac_mode_sel = 2'b00;

wire    tc_bypass;
wire    vldo;

assign    tc_bypass  =  1'b0;

reg  en;
always  @(posedge clk or negedge rstn)begin
    if(rstn==1'b0)begin
        en <= 1;
    end
    else begin
        en <= ~en;
    end
end
wire signed [15:0] dout_p[7:0];

z_dsp inst_z_dsp(
            .rstn       (rstn  ), 
            .clk       (clk  ),
            .en       (en  ),
//            .tc_bypass       (tc_bypass  ),
            .vldi_coef        (vldi_coef   ),
            .vldi_data        (vldi_data_r1   ), 
//            .intp_mode       (intp_mode  ),
//            .dac_mode_sel       (dac_mode_sel  ),
            .din0       (iir_in[0]  ),
            .din1       (iir_in[1]  ),
            .din2       (iir_in[2]  ), 
            .din3       (iir_in[3]  ),
            .a0_re      (a_re[0]    ),
            .a0_im      (a_im[0]    ),
            .b0_re      (b_re[0]    ),
            .b0_im      (b_im[0]    ),
            .a1_re      (a_re[1]    ),
            .a1_im      (a_im[1]    ),
            .b1_re      (b_re[1]    ),
            .b1_im      (b_im[1]    ),
            .a2_re      (a_re[2]    ),
            .a2_im      (a_im[2]    ),
            .b2_re      (b_re[2]    ),
            .b2_im      (b_im[2]    ),
            .a3_re      (a_re[3]    ),
            .a3_im      (a_im[3]    ),
            .b3_re      (b_re[3]    ),
            .b3_im      (b_im[3]    ),
            .a4_re      (a_re[4]    ),
            .a4_im      (a_im[4]    ),
            .b4_re      (b_re[4]    ),
            .b4_im      (b_im[4]    ),
            .a5_re      (a_re[5]    ),
            .a5_im      (a_im[5]    ),
            .b5_re      (b_re[5]    ),
            .b5_im      (b_im[5]    ),
            .dout0      (dout_p[0]  ),
            .dout1      (dout_p[1]  ),
            .dout2      (dout_p[2]  ),
            .dout3      (dout_p[3]  ),
            .vldo        ( vldo  )
            );


integer signed In_fid[0:3];
integer signed dout_fid[0:7];
string filenames_in[0:3] = {"in0.dat", "in1.dat", "in2.dat", "in3.dat"};
string filenames_dout[0:7] = {"dout0.dat", "dout1.dat", "dout2.dat", "dout3.dat", "dout4.dat", "dout5.dat", "dout6.dat", "dout7.dat"};

initial begin
    #0;
    for (int i = 0; i < 4; i = i + 1) begin
        In_fid[i] = $fopen(filenames_in[i]);
    end
    for (int i = 0; i < 4; i = i + 1) begin
        dout_fid[i] = $fopen(filenames_dout[i]);
    end
end

always @(posedge clk) begin
    if (vldi_data_r1) begin
        for (int i = 0; i < 4; i = i + 1) begin
            $fwrite(In_fid[i], "%d\n", $signed(iir_in[i]));
        end
    end
end

always @(posedge clk) begin
    if (vldo) begin
        for (int i = 0; i < 4; i = i + 1) begin
            $fwrite(dout_fid[i], "%d\n", $signed(dout_p[i]));
        end
    end
end
endmodule