//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    Z_dsp.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.2         2024-10-09      thfu            to fit the addition of 8 interpolation
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	z_dsp	 	
(
 input  rstn
,input  clk
,input  en
,input  tc_bypass
,input  vldi 
,input  [1:0]	intp_mode
,input  [1:0]	dac_mode_sel
,input  signed [15:0] din_re
,input  signed [15:0] din_im
,input  signed [31:0] a0_re
,input  signed [31:0] a0_im
,input  signed [31:0] b0_re
,input  signed [31:0] b0_im
,input  signed [31:0] a1_re
,input  signed [31:0] a1_im
,input  signed [31:0] b1_re
,input  signed [31:0] b1_im
,input  signed [31:0] a2_re
,input  signed [31:0] a2_im
,input  signed [31:0] b2_re
,input  signed [31:0] b2_im
,input  signed [31:0] a3_re
,input  signed [31:0] a3_im
,input  signed [31:0] b3_re
,input  signed [31:0] b3_im
,input  signed [31:0] a4_re
,input  signed [31:0] a4_im
,input  signed [31:0] b4_re
,input  signed [31:0] b4_im
,input  signed [31:0] a5_re
,input  signed [31:0] a5_im
,input  signed [31:0] b5_re
,input  signed [31:0] b5_im

,output signed [15:0] dout0
,output signed [15:0] dout1
,output signed [15:0] dout2
,output signed [15:0] dout3
,output		      vldo
		 	);		

parameter  Delay = 11-1;

wire signed	[15:0] IIR_out;

reg	[Delay:0]		  vldo_r;

always@(posedge clk or negedge rstn)
	if(!rstn)
		begin
			vldo_r	<=	11'b0;			
		end
	else if(en)
		begin
			vldo_r	<=	{vldo_r[Delay:0], vldi};//Delay with 9 clk		
                end
	else
		begin
			vldo_r	<=	vldo_r;		
                end


assign		vldo = vldo_r[Delay];

TailCorr_top	inst_TailCorr_top
               (
		        .clk			(clk	                ),
		        .rstn			(rstn			),
			.en			(en			),
			.tc_bypass		(tc_bypass		),
		        .din_re			(din_re                 ),
		        .din_im			(din_im                 ),
			.a0_re			(a0_re                  ),
			.a0_im			(a0_im                  ),
			.b0_re			(b0_re                  ),
			.b0_im			(b0_im                  ),
			.a1_re			(a1_re                  ),
			.a1_im			(a1_im                  ),
			.b1_re			(b1_re                  ),
			.b1_im			(b1_im                  ), 
			.a2_re			(a2_re                  ),
			.a2_im			(a2_im                  ),
			.b2_re			(b2_re                  ),
			.b2_im			(b2_im                  ),  
			.a3_re			(a3_re                  ),
			.a3_im			(a3_im                  ),
			.b3_re			(b3_re                  ),
			.b3_im			(b3_im                  ),
			.a4_re			(a4_re                  ),
			.a4_im			(a4_im                  ),
			.b4_re			(b4_re                  ),
			.b4_im			(b4_im                  ), 
			.a5_re			(a5_re                  ),
			.a5_im			(a5_im                  ),
			.b5_re			(b5_re                  ),
			.b5_im			(b5_im                  ),                         
		        .dout			(IIR_out                )
                );

wire signed	[15:0] dout_0;
wire signed	[15:0] dout_1;
wire signed	[15:0] dout_2;
wire signed	[15:0] dout_3;
wire signed	[15:0] dout_4;
wire signed	[15:0] dout_5;
wire signed	[15:0] dout_6;
wire signed	[15:0] dout_7;


MeanIntp_8		inst_MeanIntp_8
		       (
			.clk				(clk		        ),
			.rstn				(rstn			),
			.en				(en			),
			.intp_mode			(intp_mode		),
                        .din	                	(IIR_out		),           
			.dout_0				(dout_0        	        ),
			.dout_1				(dout_1          	),
			.dout_2				(dout_2          	),
			.dout_3				(dout_3           	),
			.dout_4				(dout_4        	        ),
			.dout_5				(dout_5          	),
			.dout_6				(dout_6          	),
			.dout_7				(dout_7           	)

		        );

reg signed [15:0]	doutf_0;
reg signed [15:0]	doutf_1;	
reg signed [15:0]	doutf_2;	
reg signed [15:0]	doutf_3;

always@(posedge clk or negedge rstn)
    if(!rstn)  begin
    		doutf_0  <=  0;
    		doutf_1  <=  0;	
    		doutf_2  <=  0;	
    		doutf_3  <=  0;	
    end
    else if(en)  begin
    		doutf_0  <=  dout_0;
    		doutf_1  <=  dout_1;	
    		doutf_2  <=  dout_2;	
    		doutf_3  <=  dout_3;	
    end 
    else  begin
    		doutf_0  <=  dout_4;
    		doutf_1  <=  dout_5;	
    		doutf_2  <=  dout_6;	
    		doutf_3  <=  dout_7;	
    end
    
assign    dout0  =  doutf_0; 
assign    dout1  =  doutf_1;
assign    dout2  =  doutf_2;
assign    dout3  =  doutf_3;

endmodule