module FixRound #(
 parameter    integer    Data_width = 8
,parameter    integer    Fix_frac_coef_width = 31//division

)
(
 input                                    clk
,input                                    rstn
,input                                    en
,input       signed  [Data_width-1:0]     din
,output      signed  [Data_width-1:0]     dout
);

reg         signed  [Data_width-1:0]     din_round;

always@(posedge clk or negedge rstn)
	if(!rstn)
		begin
				din_round  <=	'h0;
		end
	else  if(en)  begin
		if(din[Data_width-1] == 1'b0)
			begin
				din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}};
			end
		else if (din[Data_width-1] == 1'b1)
			begin	
				din_round <= din + {{1'b1},{(Fix_frac_coef_width-1){1'b0}}} - 1'b1;
			end
	end
	else  begin
		din_round <=  din_round;
	end

assign	dout = din_round;

endmodule