module	PIPE3_ACC_48BIT(
	clk,
	rstn,
	in,
	clr,
	ptw,	
	s_i_1,
	s_i_2,
	s_i_3,
	s_o_1,
	s_o_2,
	s_o_3,
	out
);

//---

  input			clk;
  input			rstn;
  input		[47:0]	in;
  input			clr;
  input		[15:0]	ptw;

  input		[15:0]	s_i_1;
  input		[15:0]	s_i_2;
  input		[15:0]	s_i_3;

  output	[15:0]	s_o_1;
  output	[15:0]	s_o_2;
  output	[15:0]	s_o_3;
  output	[18:0]	out;

//----------------------------------------------------------------------------------------------------

 reg	[47:0]	acc;
   always@(posedge clk or negedge rstn)
      if(!rstn)
		acc<=48'h0;
      else if(clr)
	      	acc<=48'h0;
      else
	      	acc<={s_i_1,s_i_2,s_i_3}+in;


//----------------------------------------------------------------------------------------------------
  wire	[15:0]	s1;
  wire	[15:0]	s2;
  wire	[15:0]	s3;

  assign	s_o_1 = acc[47:32];
  assign	s_o_2 = acc[31:16];
  assign	s_o_3 = acc[15:0];

  wire[18:0]	pha_w;
  assign          pha_w=acc[47:29];
  reg[18:0]	pha_r;
  always@(posedge clk)
			pha_r<=pha_w+{ptw,3'b0};

 assign	out=pha_r;
//END
endmodule