module s2p_2 (
    input  clk,             
    input  rst_n,            
    input  [15:0] din, 
    input   en,          
    output  [15:0] dout0,    
    output  [15:0] dout1,     
    output  vldo     
);

reg en_r1;
reg en_r2;

always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        en_r1 <= 0;
        en_r2 <= 0;
    end
    else begin
        en_r1 <= en;
        en_r2 <= en_r1;
    end
end
assign  vldo  = en_r2;

reg cnt;
wire add_cnt;
wire end_cnt;

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        cnt <= 0;
    end
    else if(add_cnt)begin
        if(end_cnt)
            cnt <= 0;
        else
            cnt <= cnt + 1;
    end
    else begin
        cnt <= 0;
    end
end

assign add_cnt = en == 1'b1;       
assign end_cnt = add_cnt && cnt== 2 - 1 ;  


reg   [   15: 0]         dout0_r0;
reg   [   15: 0]         dout1_r0;
wire            dout0_en;
wire            dout1_en;
wire            dout0_hold;
wire            dout1_hold;

always  @(*)begin
    if(rst_n==1'b0)begin
        dout0_r0  =  16'd0;
        dout1_r0  =  16'd0;
    end
    else if(dout0_en)begin
        dout0_r0  =  din;
    end
    else if(dout1_en)begin
        dout1_r0  =  din;
    end
    else begin
        dout0_r0  =  16'd0;
        dout1_r0  =  16'd0;

    end
end
assign  dout0_en = add_cnt && cnt == 0;
assign  dout1_en = add_cnt && cnt == 1;

reg   [   15: 0]         dout0_r1;
reg   [   15: 0]         dout1_r1;
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        dout0_r1  <=  16'd0;
        dout1_r1  <=  16'd0;
    end
    else if(en)begin
        dout0_r1  <=  dout0_r0;
        dout1_r1  <=  dout1_r0;
    end
    else if(dout0_hold)begin
        dout0_r1  <=  dout0_r1;
        dout1_r1  <=  16'd0;
    end
    else if(dout1_hold)begin
        dout0_r1  <=  16'd0;
        dout1_r1  <=  dout1_r1;
    end
    else begin
        dout0_r1  <=  16'd0;
        dout1_r1  <=  16'd0;
    end

end
assign  dout0_hold = en == 0 && en_r1 == 1 && cnt == 1;
assign  dout1_hold = en == 0 && en_r1 == 1 && cnt == 0;

reg   [   15: 0]         dout0_r2;
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin        
        dout0_r2  <=  16'd0;
    end
    else begin
        dout0_r2  <=  dout0_r1;
    end
end

assign dout0 = dout0_r2;
assign dout1 = dout1_r1;


endmodule