//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
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//  File Name             :    mult_C.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-28      thfu
//2024-05-28 10:22:18 
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
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//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_x #(
 parameter    integer    A_width = 8
,parameter    integer    C_width = 8
,parameter    integer    D_width = 8
,parameter    integer    o_width = 31//division

)

(
            clk,
            rstn,
            en,
            a,
	    c,
	    d,
	    Re,
	    Im
);

input       rstn;
input       clk;
input       en;
input       signed  [A_width-1        :0]	a;
input       signed  [C_width-1        :0]	c;
input       signed  [D_width-1        :0]	d;

output      signed  [o_width-1        :0]	Re;
output      signed  [o_width-1        :0]	Im;

wire	    signed  [A_width+C_width-1:0]	ac;
wire	    signed  [A_width+D_width-1:0]	ad;
wire        signed  [o_width-1        :0]	Re_trunc;
wire        signed  [o_width-1        :0]	Im_trunc;



DW02_mult	#(A_width,C_width) inst_c1(	.A		(a		),
						.B		(c		),
						.TC		(1'b1		),
						.PRODUCT	(ac		)
				);

DW02_mult	#(A_width,D_width) inst_c3(	.A		(a		),
						.B		(d		),
						.TC		(1'b1		),
						.PRODUCT	(ad		)
				);



trunc #(
	 .diw	(A_width+C_width		)
	,.msb	(A_width+C_width-2		)
	,.lsb	(A_width+C_width-o_width-1 	)
) u_round1 (clk, rstn, en, ac, Re_trunc);
trunc #(
	 .diw	(A_width+D_width		)
	,.msb	(A_width+D_width-2		)
	,.lsb	(A_width+D_width-o_width-1	)
) u_round2 (clk, rstn, en, ad, Im_trunc);

// Since this is complex multiplication, the output bit width needs to be increased by one compared to the input.
assign	Re = Re_trunc;
assign	Im = Im_trunc;

endmodule