module trunc #(
 parameter    integer    diw = 8
//,parameter    integer    dow = msb - (lsb -1)
,parameter    integer    msb = 7
,parameter    integer    lsb = 1
)
(
 input                                      clk
,input                                      rstn
,input                                      en
,input       signed  [diw - 1  :0]     	    din
,output      signed  [msb - lsb:0]          dout
);


reg	signed [msb  -  lsb : 0]	d_tmp;

generate
	if(lsb==0) begin
		always @(posedge clk or negedge rstn) begin
        		if (!rstn) begin
                 		d_tmp 	<= 	'h0;
                 	end 
         		else if(en) begin
                 		if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
                 		    d_tmp	<=	{{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
		 		else
		     		    d_tmp	<=      din[msb:lsb];
		 	end
         		else begin
                     		d_tmp	<=	d_tmp;
                 	end
		end
	end
	else begin
		always @(posedge clk or negedge rstn) begin
        		if (!rstn) begin
                 		d_tmp 	<= 	'h0;
                 	end 
         		else if(en) begin
                 		if(din[diw-1 : msb] != {(diw-msb){din[diw-1]}})
                 		    d_tmp	<=	{{din[diw-1]}, {(msb-lsb){!din[diw-1]}}};
		 		else
		     		    d_tmp	<=      din[msb:lsb] + {{(msb-lsb){1'b0}},din[lsb-1]};
		 	end
         		else begin
                     		d_tmp	<=	d_tmp;
                 	end
		end
	end
endgenerate

assign dout = d_tmp;

endmodule