module 	rate_adapter	 	
(
 input                  rstn
,input                  clk
,input                  en
,input                  vldi
,input  signed [15:0]   din0
,input  signed [15:0]   din1
,input  signed [15:0]   din2
,input  signed [15:0]   din3
,input  signed [15:0]   din4
,input  signed [15:0]   din5
,input  signed [15:0]   din6
,input  signed [15:0]   din7
,output signed [15:0]   dout0
,output signed [15:0]   dout1
,output signed [15:0]   dout2
,output signed [15:0]   dout3
,output                 vldo
		 	);		



reg signed [15:0]	doutf_0;
reg signed [15:0]	doutf_1;	
reg signed [15:0]	doutf_2;	
reg signed [15:0]	doutf_3;

always@(posedge clk or negedge rstn)
    if(!rstn)  begin
    		doutf_0  <=  0;
    		doutf_1  <=  0;	
    		doutf_2  <=  0;	
    		doutf_3  <=  0;	
    end
    else if(!en)  begin
    		doutf_0  <=  din0;
    		doutf_1  <=  din1;	
    		doutf_2  <=  din2;	
    		doutf_3  <=  din3;	
    end 
    else  begin
    		doutf_0  <=  din4;
    		doutf_1  <=  din5;	
    		doutf_2  <=  din6;	
    		doutf_3  <=  din7;	
    end
    
assign    dout0  =  doutf_0; 
assign    dout1  =  doutf_1;
assign    dout2  =  doutf_2;
assign    dout3  =  doutf_3;

//sirv_gnrl_dffr #(1) dff_vldi_or_1(vldi, vldo ,clk,rstn);
assign    vldo = vldi;
endmodule