//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : TailCorr_top.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.3 2025-02-28 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module TailCorr_top ( input rstn ,input clk ,input en ,input vldi ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31:0] a_re0 ,input signed [31:0] a_im0 ,input signed [31:0] ab_re0 ,input signed [31:0] ab_im0 ,input signed [31:0] abb_re0 ,input signed [31:0] abb_im0 ,input signed [31:0] ab_pow3_re0 ,input signed [31:0] ab_pow3_im0 ,input signed [31:0] ab_pow4_re0 ,input signed [31:0] ab_pow4_im0 ,input signed [31:0] ab_pow5_re0 ,input signed [31:0] ab_pow5_im0 ,input signed [31:0] ab_pow6_re0 ,input signed [31:0] ab_pow6_im0 ,input signed [31:0] ab_pow7_re0 ,input signed [31:0] ab_pow7_im0 ,input signed [31:0] b_pow8_re0 ,input signed [31:0] b_pow8_im0 ,input signed [31:0] a_re1 ,input signed [31:0] a_im1 ,input signed [31:0] ab_re1 ,input signed [31:0] ab_im1 ,input signed [31:0] abb_re1 ,input signed [31:0] abb_im1 ,input signed [31:0] ab_pow3_re1 ,input signed [31:0] ab_pow3_im1 ,input signed [31:0] ab_pow4_re1 ,input signed [31:0] ab_pow4_im1 ,input signed [31:0] ab_pow5_re1 ,input signed [31:0] ab_pow5_im1 ,input signed [31:0] ab_pow6_re1 ,input signed [31:0] ab_pow6_im1 ,input signed [31:0] ab_pow7_re1 ,input signed [31:0] ab_pow7_im1 ,input signed [31:0] b_pow8_re1 ,input signed [31:0] b_pow8_im1 ,input signed [31:0] a_re2 ,input signed [31:0] a_im2 ,input signed [31:0] ab_re2 ,input signed [31:0] ab_im2 ,input signed [31:0] abb_re2 ,input signed [31:0] abb_im2 ,input signed [31:0] ab_pow3_re2 ,input signed [31:0] ab_pow3_im2 ,input signed [31:0] ab_pow4_re2 ,input signed [31:0] ab_pow4_im2 ,input signed [31:0] ab_pow5_re2 ,input signed [31:0] ab_pow5_im2 ,input signed [31:0] ab_pow6_re2 ,input signed [31:0] ab_pow6_im2 ,input signed [31:0] ab_pow7_re2 ,input signed [31:0] ab_pow7_im2 ,input signed [31:0] b_pow8_re2 ,input signed [31:0] b_pow8_im2 ,input signed [31:0] a_re3 ,input signed [31:0] a_im3 ,input signed [31:0] ab_re3 ,input signed [31:0] ab_im3 ,input signed [31:0] abb_re3 ,input signed [31:0] abb_im3 ,input signed [31:0] ab_pow3_re3 ,input signed [31:0] ab_pow3_im3 ,input signed [31:0] ab_pow4_re3 ,input signed [31:0] ab_pow4_im3 ,input signed [31:0] ab_pow5_re3 ,input signed [31:0] ab_pow5_im3 ,input signed [31:0] ab_pow6_re3 ,input signed [31:0] ab_pow6_im3 ,input signed [31:0] ab_pow7_re3 ,input signed [31:0] ab_pow7_im3 ,input signed [31:0] b_pow8_re3 ,input signed [31:0] b_pow8_im3 ,input signed [31:0] a_re4 ,input signed [31:0] a_im4 ,input signed [31:0] ab_re4 ,input signed [31:0] ab_im4 ,input signed [31:0] abb_re4 ,input signed [31:0] abb_im4 ,input signed [31:0] ab_pow3_re4 ,input signed [31:0] ab_pow3_im4 ,input signed [31:0] ab_pow4_re4 ,input signed [31:0] ab_pow4_im4 ,input signed [31:0] ab_pow5_re4 ,input signed [31:0] ab_pow5_im4 ,input signed [31:0] ab_pow6_re4 ,input signed [31:0] ab_pow6_im4 ,input signed [31:0] ab_pow7_re4 ,input signed [31:0] ab_pow7_im4 ,input signed [31:0] b_pow8_re4 ,input signed [31:0] b_pow8_im4 ,input signed [31:0] a_re5 ,input signed [31:0] a_im5 ,input signed [31:0] ab_re5 ,input signed [31:0] ab_im5 ,input signed [31:0] abb_re5 ,input signed [31:0] abb_im5 ,input signed [31:0] ab_pow3_re5 ,input signed [31:0] ab_pow3_im5 ,input signed [31:0] ab_pow4_re5 ,input signed [31:0] ab_pow4_im5 ,input signed [31:0] ab_pow5_re5 ,input signed [31:0] ab_pow5_im5 ,input signed [31:0] ab_pow6_re5 ,input signed [31:0] ab_pow6_im5 ,input signed [31:0] ab_pow7_re5 ,input signed [31:0] ab_pow7_im5 ,input signed [31:0] b_pow8_re5 ,input signed [31:0] b_pow8_im5 ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 ,output signed [15:0] dout_p2 ,output signed [15:0] dout_p3 ,output signed [15:0] dout_p4 ,output signed [15:0] dout_p5 ,output signed [15:0] dout_p6 ,output signed [15:0] dout_p7 ,output vldo ); wire signed [15:0] din_p0; wire signed [15:0] din_p1; wire signed [15:0] din_p2; wire signed [15:0] din_p3; wire signed [15:0] din_p4; wire signed [15:0] din_p5; wire signed [15:0] din_p6; wire signed [15:0] din_p7; wire signed [15:0] IIRin_p0; wire signed [15:0] IIRin_p1; wire signed [15:0] IIRin_p2; wire signed [15:0] IIRin_p3; wire signed [15:0] IIRin_p4; wire signed [15:0] IIRin_p5; wire signed [15:0] IIRin_p6; wire signed [15:0] IIRin_p7; wire vldo_diff; diff_p inst_diff_p ( .rstn (rstn), .clk (clk ), .en (en ), .vldi (vldi), .din0 (din0), .din1 (din1), .din2 (din2), .din3 (din3), .vldo (vldo_diff), .dout_p0 (din_p0), .dout_p1 (din_p1), .dout_p2 (din_p2), .dout_p3 (din_p3), .dout_p4 (din_p4), .dout_p5 (din_p5), .dout_p6 (din_p6), .dout_p7 (din_p7), .diff_p0 (IIRin_p0), .diff_p1 (IIRin_p1), .diff_p2 (IIRin_p2), .diff_p3 (IIRin_p3), .diff_p4 (IIRin_p4), .diff_p5 (IIRin_p5), .diff_p6 (IIRin_p6), .diff_p7 (IIRin_p7) ); reg signed [15:0] din_p0_r1; reg signed [15:0] din_p0_r2; reg signed [15:0] din_p0_r3; reg signed [15:0] din_p0_r4; reg signed [15:0] din_p0_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p0_r1 <= 'h0; din_p0_r2 <= 'h0; din_p0_r3 <= 'h0; din_p0_r4 <= 'h0; din_p0_r5 <= 'h0; end else if(en) begin din_p0_r1 <= din_p0; din_p0_r2 <= din_p0_r1; din_p0_r3 <= din_p0_r2; din_p0_r4 <= din_p0_r3; din_p0_r5 <= din_p0_r4; end else begin din_p0_r1 <= din_p0_r1; din_p0_r2 <= din_p0_r2; din_p0_r3 <= din_p0_r3; din_p0_r4 <= din_p0_r4; din_p0_r5 <= din_p0_r5; end reg signed [15:0] din_p1_r1; reg signed [15:0] din_p1_r2; reg signed [15:0] din_p1_r3; reg signed [15:0] din_p1_r4; reg signed [15:0] din_p1_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p1_r1 <= 'h0; din_p1_r2 <= 'h0; din_p1_r3 <= 'h0; din_p1_r4 <= 'h0; din_p1_r5 <= 'h0; end else if(en) begin din_p1_r1 <= din_p1; din_p1_r2 <= din_p1_r1; din_p1_r3 <= din_p1_r2; din_p1_r4 <= din_p1_r3; din_p1_r5 <= din_p1_r4; end else begin din_p1_r1 <= din_p1_r1; din_p1_r2 <= din_p1_r2; din_p1_r3 <= din_p1_r3; din_p1_r4 <= din_p1_r4; din_p1_r5 <= din_p1_r5; end reg signed [15:0] din_p2_r1; reg signed [15:0] din_p2_r2; reg signed [15:0] din_p2_r3; reg signed [15:0] din_p2_r4; reg signed [15:0] din_p2_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p2_r1 <= 'h0; din_p2_r2 <= 'h0; din_p2_r3 <= 'h0; din_p2_r4 <= 'h0; din_p2_r5 <= 'h0; end else if(en) begin din_p2_r1 <= din_p2; din_p2_r2 <= din_p2_r1; din_p2_r3 <= din_p2_r2; din_p2_r4 <= din_p2_r3; din_p2_r5 <= din_p2_r4; end else begin din_p2_r1 <= din_p2_r1; din_p2_r2 <= din_p2_r2; din_p2_r3 <= din_p2_r3; din_p2_r4 <= din_p2_r4; din_p2_r5 <= din_p2_r5; end reg signed [15:0] din_p3_r1; reg signed [15:0] din_p3_r2; reg signed [15:0] din_p3_r3; reg signed [15:0] din_p3_r4; reg signed [15:0] din_p3_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p3_r1 <= 'h0; din_p3_r2 <= 'h0; din_p3_r3 <= 'h0; din_p3_r4 <= 'h0; din_p3_r5 <= 'h0; end else if(en) begin din_p3_r1 <= din_p3; din_p3_r2 <= din_p3_r1; din_p3_r3 <= din_p3_r2; din_p3_r4 <= din_p3_r3; din_p3_r5 <= din_p3_r4; end else begin din_p3_r1 <= din_p3_r1; din_p3_r2 <= din_p3_r2; din_p3_r3 <= din_p3_r3; din_p3_r4 <= din_p3_r4; din_p3_r5 <= din_p3_r5; end reg signed [15:0] din_p4_r1; reg signed [15:0] din_p4_r2; reg signed [15:0] din_p4_r3; reg signed [15:0] din_p4_r4; reg signed [15:0] din_p4_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p4_r1 <= 'h0; din_p4_r2 <= 'h0; din_p4_r3 <= 'h0; din_p4_r4 <= 'h0; din_p4_r5 <= 'h0; end else if(en) begin din_p4_r1 <= din_p4; din_p4_r2 <= din_p4_r1; din_p4_r3 <= din_p4_r2; din_p4_r4 <= din_p4_r3; din_p4_r5 <= din_p4_r4; end else begin din_p4_r1 <= din_p4_r1; din_p4_r2 <= din_p4_r2; din_p4_r3 <= din_p4_r3; din_p4_r4 <= din_p4_r4; din_p4_r5 <= din_p4_r5; end reg signed [15:0] din_p5_r1; reg signed [15:0] din_p5_r2; reg signed [15:0] din_p5_r3; reg signed [15:0] din_p5_r4; reg signed [15:0] din_p5_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p5_r1 <= 'h0; din_p5_r2 <= 'h0; din_p5_r3 <= 'h0; din_p5_r4 <= 'h0; din_p5_r5 <= 'h0; end else if(en) begin din_p5_r1 <= din_p5; din_p5_r2 <= din_p5_r1; din_p5_r3 <= din_p5_r2; din_p5_r4 <= din_p5_r3; din_p5_r5 <= din_p5_r4; end else begin din_p5_r1 <= din_p5_r1; din_p5_r2 <= din_p5_r2; din_p5_r3 <= din_p5_r3; din_p5_r4 <= din_p5_r4; din_p5_r5 <= din_p5_r5; end reg signed [15:0] din_p6_r1; reg signed [15:0] din_p6_r2; reg signed [15:0] din_p6_r3; reg signed [15:0] din_p6_r4; reg signed [15:0] din_p6_r5; always @(posedge clk or negedge rstn) if (!rstn) begin din_p6_r1 <= 'h0; din_p6_r2 <= 'h0; din_p6_r3 <= 'h0; din_p6_r4 <= 'h0; din_p6_r5 <= 'h0; end else if(en) begin din_p6_r1 <= din_p6; din_p6_r2 <= din_p6_r1; din_p6_r3 <= din_p6_r2; din_p6_r4 <= din_p6_r3; din_p6_r5 <= din_p6_r4; end else begin din_p6_r1 <= din_p6_r1; din_p6_r2 <= din_p6_r2; din_p6_r3 <= din_p6_r3; din_p6_r4 <= din_p6_r4; din_p6_r5 <= din_p6_r5; end reg signed [15:0] din_p7_r1; reg signed [15:0] din_p7_r2; reg signed [15:0] din_p7_r3; reg signed [15:0] din_p7_r4; reg signed [15:0] din_p7_r5; reg signed [15:0] din_p7_r6; always @(posedge clk or negedge rstn) if (!rstn) begin din_p7_r1 <= 'h0; din_p7_r2 <= 'h0; din_p7_r3 <= 'h0; din_p7_r4 <= 'h0; din_p7_r5 <= 'h0; end else if(en) begin din_p7_r1 <= din_p7; din_p7_r2 <= din_p7_r1; din_p7_r3 <= din_p7_r2; din_p7_r4 <= din_p7_r3; din_p7_r5 <= din_p7_r4; end else begin din_p7_r1 <= din_p7_r1; din_p7_r2 <= din_p7_r2; din_p7_r3 <= din_p7_r3; din_p7_r4 <= din_p7_r4; din_p7_r5 <= din_p7_r5; end wire signed [15:0] IIRout0_p0; wire signed [15:0] IIRout0_p1; wire signed [15:0] IIRout0_p2; wire signed [15:0] IIRout0_p3; wire signed [15:0] IIRout0_p4; wire signed [15:0] IIRout0_p5; wire signed [15:0] IIRout0_p6; wire signed [15:0] IIRout0_p7; IIR_top inst_iir_top_0 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re0 ), .a_im (a_im0 ), .ab_re (ab_re0 ), .ab_im (ab_im0 ), .abb_re (abb_re0 ), .abb_im (abb_im0 ), .ab_pow3_re (ab_pow3_re0 ), .ab_pow3_im (ab_pow3_im0 ), .ab_pow4_re (ab_pow4_re0 ), .ab_pow4_im (ab_pow4_im0 ), .ab_pow5_re (ab_pow5_re0 ), .ab_pow5_im (ab_pow5_im0 ), .ab_pow6_re (ab_pow6_re0 ), .ab_pow6_im (ab_pow6_im0 ), .ab_pow7_re (ab_pow7_re0 ), .ab_pow7_im (ab_pow7_im0 ), .b_pow8_re (b_pow8_re0 ), .b_pow8_im (b_pow8_im0 ), .IIRout_p0 (IIRout0_p0 ), .IIRout_p1 (IIRout0_p1 ), .IIRout_p2 (IIRout0_p2 ), .IIRout_p3 (IIRout0_p3 ), .IIRout_p4 (IIRout0_p4 ), .IIRout_p5 (IIRout0_p5 ), .IIRout_p6 (IIRout0_p6 ), .IIRout_p7 (IIRout0_p7 ) ); wire signed [15:0] IIRout1_p0; wire signed [15:0] IIRout1_p1; wire signed [15:0] IIRout1_p2; wire signed [15:0] IIRout1_p3; wire signed [15:0] IIRout1_p4; wire signed [15:0] IIRout1_p5; wire signed [15:0] IIRout1_p6; wire signed [15:0] IIRout1_p7; IIR_top inst_iir_top_1 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re1 ), .a_im (a_im1 ), .ab_re (ab_re1 ), .ab_im (ab_im1 ), .abb_re (abb_re1 ), .abb_im (abb_im1 ), .ab_pow3_re (ab_pow3_re1 ), .ab_pow3_im (ab_pow3_im1 ), .ab_pow4_re (ab_pow4_re1 ), .ab_pow4_im (ab_pow4_im1 ), .ab_pow5_re (ab_pow5_re1 ), .ab_pow5_im (ab_pow5_im1 ), .ab_pow6_re (ab_pow6_re1 ), .ab_pow6_im (ab_pow6_im1 ), .ab_pow7_re (ab_pow7_re1 ), .ab_pow7_im (ab_pow7_im1 ), .b_pow8_re (b_pow8_re1 ), .b_pow8_im (b_pow8_im1 ), .IIRout_p0 (IIRout1_p0 ), .IIRout_p1 (IIRout1_p1 ), .IIRout_p2 (IIRout1_p2 ), .IIRout_p3 (IIRout1_p3 ), .IIRout_p4 (IIRout1_p4 ), .IIRout_p5 (IIRout1_p5 ), .IIRout_p6 (IIRout1_p6 ), .IIRout_p7 (IIRout1_p7 ) ); wire signed [15:0] IIRout2_p0; wire signed [15:0] IIRout2_p1; wire signed [15:0] IIRout2_p2; wire signed [15:0] IIRout2_p3; wire signed [15:0] IIRout2_p4; wire signed [15:0] IIRout2_p5; wire signed [15:0] IIRout2_p6; wire signed [15:0] IIRout2_p7; IIR_top inst_iir_top_2 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re2 ), .a_im (a_im2 ), .ab_re (ab_re2 ), .ab_im (ab_im2 ), .abb_re (abb_re2 ), .abb_im (abb_im2 ), .ab_pow3_re (ab_pow3_re2 ), .ab_pow3_im (ab_pow3_im2 ), .ab_pow4_re (ab_pow4_re2 ), .ab_pow4_im (ab_pow4_im2 ), .ab_pow5_re (ab_pow5_re2 ), .ab_pow5_im (ab_pow5_im2 ), .ab_pow6_re (ab_pow6_re2 ), .ab_pow6_im (ab_pow6_im2 ), .ab_pow7_re (ab_pow7_re2 ), .ab_pow7_im (ab_pow7_im2 ), .b_pow8_re (b_pow8_re2 ), .b_pow8_im (b_pow8_im2 ), .IIRout_p0 (IIRout2_p0 ), .IIRout_p1 (IIRout2_p1 ), .IIRout_p2 (IIRout2_p2 ), .IIRout_p3 (IIRout2_p3 ), .IIRout_p4 (IIRout2_p4 ), .IIRout_p5 (IIRout2_p5 ), .IIRout_p6 (IIRout2_p6 ), .IIRout_p7 (IIRout2_p7 ) ); wire signed [15:0] IIRout3_p0; wire signed [15:0] IIRout3_p1; wire signed [15:0] IIRout3_p2; wire signed [15:0] IIRout3_p3; wire signed [15:0] IIRout3_p4; wire signed [15:0] IIRout3_p5; wire signed [15:0] IIRout3_p6; wire signed [15:0] IIRout3_p7; IIR_top inst_iir_top_3 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re3 ), .a_im (a_im3 ), .ab_re (ab_re3 ), .ab_im (ab_im3 ), .abb_re (abb_re3 ), .abb_im (abb_im3 ), .ab_pow3_re (ab_pow3_re3 ), .ab_pow3_im (ab_pow3_im3 ), .ab_pow4_re (ab_pow4_re3 ), .ab_pow4_im (ab_pow4_im3 ), .ab_pow5_re (ab_pow5_re3 ), .ab_pow5_im (ab_pow5_im3 ), .ab_pow6_re (ab_pow6_re3 ), .ab_pow6_im (ab_pow6_im3 ), .ab_pow7_re (ab_pow7_re3 ), .ab_pow7_im (ab_pow7_im3 ), .b_pow8_re (b_pow8_re3 ), .b_pow8_im (b_pow8_im3 ), .IIRout_p0 (IIRout3_p0 ), .IIRout_p1 (IIRout3_p1 ), .IIRout_p2 (IIRout3_p2 ), .IIRout_p3 (IIRout3_p3 ), .IIRout_p4 (IIRout3_p4 ), .IIRout_p5 (IIRout3_p5 ), .IIRout_p6 (IIRout3_p6 ), .IIRout_p7 (IIRout3_p7 ) ); wire signed [15:0] IIRout4_p0; wire signed [15:0] IIRout4_p1; wire signed [15:0] IIRout4_p2; wire signed [15:0] IIRout4_p3; wire signed [15:0] IIRout4_p4; wire signed [15:0] IIRout4_p5; wire signed [15:0] IIRout4_p6; wire signed [15:0] IIRout4_p7; IIR_top inst_iir_top_4 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re4 ), .a_im (a_im4 ), .ab_re (ab_re4 ), .ab_im (ab_im4 ), .abb_re (abb_re4 ), .abb_im (abb_im4 ), .ab_pow3_re (ab_pow3_re4 ), .ab_pow3_im (ab_pow3_im4 ), .ab_pow4_re (ab_pow4_re4 ), .ab_pow4_im (ab_pow4_im4 ), .ab_pow5_re (ab_pow5_re4 ), .ab_pow5_im (ab_pow5_im4 ), .ab_pow6_re (ab_pow6_re4 ), .ab_pow6_im (ab_pow6_im4 ), .ab_pow7_re (ab_pow7_re4 ), .ab_pow7_im (ab_pow7_im4 ), .b_pow8_re (b_pow8_re4 ), .b_pow8_im (b_pow8_im4 ), .IIRout_p0 (IIRout4_p0 ), .IIRout_p1 (IIRout4_p1 ), .IIRout_p2 (IIRout4_p2 ), .IIRout_p3 (IIRout4_p3 ), .IIRout_p4 (IIRout4_p4 ), .IIRout_p5 (IIRout4_p5 ), .IIRout_p6 (IIRout4_p6 ), .IIRout_p7 (IIRout4_p7 ) ); wire signed [15:0] IIRout5_p0; wire signed [15:0] IIRout5_p1; wire signed [15:0] IIRout5_p2; wire signed [15:0] IIRout5_p3; wire signed [15:0] IIRout5_p4; wire signed [15:0] IIRout5_p5; wire signed [15:0] IIRout5_p6; wire signed [15:0] IIRout5_p7; IIR_top inst_iir_top_5 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .a_re (a_re5 ), .a_im (a_im5 ), .ab_re (ab_re5 ), .ab_im (ab_im5 ), .abb_re (abb_re5 ), .abb_im (abb_im5 ), .ab_pow3_re (ab_pow3_re5 ), .ab_pow3_im (ab_pow3_im5 ), .ab_pow4_re (ab_pow4_re5 ), .ab_pow4_im (ab_pow4_im5 ), .ab_pow5_re (ab_pow5_re5 ), .ab_pow5_im (ab_pow5_im5 ), .ab_pow6_re (ab_pow6_re5 ), .ab_pow6_im (ab_pow6_im5 ), .ab_pow7_re (ab_pow7_re5 ), .ab_pow7_im (ab_pow7_im5 ), .b_pow8_re (b_pow8_re5 ), .b_pow8_im (b_pow8_im5 ), .IIRout_p0 (IIRout5_p0 ), .IIRout_p1 (IIRout5_p1 ), .IIRout_p2 (IIRout5_p2 ), .IIRout_p3 (IIRout5_p3 ), .IIRout_p4 (IIRout5_p4 ), .IIRout_p5 (IIRout5_p5 ), .IIRout_p6 (IIRout5_p6 ), .IIRout_p7 (IIRout5_p7 ) ); wire signed [18:0] dout_p0_r0; wire signed [18:0] dout_p1_r0; wire signed [18:0] dout_p2_r0; wire signed [18:0] dout_p3_r0; wire signed [18:0] dout_p4_r0; wire signed [18:0] dout_p5_r0; wire signed [18:0] dout_p6_r0; wire signed [18:0] dout_p7_r0; assign dout_p0_r0 = din_p0_r5 + IIRout0_p0 + IIRout1_p0 +IIRout2_p0 +IIRout3_p0 +IIRout4_p0 +IIRout5_p0; assign dout_p1_r0 = din_p1_r5 + IIRout0_p1 + IIRout1_p1 +IIRout2_p1 +IIRout3_p1 +IIRout4_p1 +IIRout5_p1; assign dout_p2_r0 = din_p2_r5 + IIRout0_p2 + IIRout1_p2 +IIRout2_p2 +IIRout3_p2 +IIRout4_p2 +IIRout5_p2; assign dout_p3_r0 = din_p3_r5 + IIRout0_p3 + IIRout1_p3 +IIRout2_p3 +IIRout3_p3 +IIRout4_p3 +IIRout5_p3; assign dout_p4_r0 = din_p4_r5 + IIRout0_p4 + IIRout1_p4 +IIRout2_p4 +IIRout3_p4 +IIRout4_p4 +IIRout5_p4; assign dout_p5_r0 = din_p5_r5 + IIRout0_p5 + IIRout1_p5 +IIRout2_p5 +IIRout3_p5 +IIRout4_p5 +IIRout5_p5; assign dout_p6_r0 = din_p6_r5 + IIRout0_p6 + IIRout1_p6 +IIRout2_p6 +IIRout3_p6 +IIRout4_p6 +IIRout5_p6; assign dout_p7_r0 = din_p7_r5 + IIRout0_p7 + IIRout1_p7 +IIRout2_p7 +IIRout3_p7 +IIRout4_p7 +IIRout5_p7; reg signed [18:0] dout_p0_r1; reg signed [18:0] dout_p1_r1; reg signed [18:0] dout_p2_r1; reg signed [18:0] dout_p3_r1; reg signed [18:0] dout_p4_r1; reg signed [18:0] dout_p5_r1; reg signed [18:0] dout_p6_r1; reg signed [18:0] dout_p7_r1; reg signed [15:0] dout_p [7:0]; wire signed [18:0] dout_p_r0 [0:7] = {dout_p0_r0,dout_p1_r0,dout_p2_r0,dout_p3_r0,dout_p4_r0,dout_p5_r0,dout_p6_r0,dout_p7_r0}; integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin for (i = 0; i < 8; i = i + 1) begin dout_p[i] <= 'h0; end end else if (en) begin for (i = 0; i < 8; i = i + 1) begin if (dout_p_r0[i][16:15] == 2'b01) dout_p[i] <= 16'd32767; else if (dout_p_r0[i][16:15] == 2'b10) dout_p[i] <= -16'd32768; else dout_p[i] <= dout_p_r0[i][15:0]; end end end assign dout_p0 = dout_p[0]; assign dout_p1 = dout_p[1]; assign dout_p2 = dout_p[2]; assign dout_p3 = dout_p[3]; assign dout_p4 = dout_p[4]; assign dout_p5 = dout_p[5]; assign dout_p6 = dout_p[6]; assign dout_p7 = dout_p[7]; always @(posedge clk or negedge rstn) if (!rstn) begin dout_p0_r1 <= 16'd0; dout_p1_r1 <= 16'd0; dout_p2_r1 <= 16'd0; dout_p3_r1 <= 16'd0; dout_p4_r1 <= 16'd0; dout_p5_r1 <= 16'd0; dout_p6_r1 <= 16'd0; dout_p7_r1 <= 16'd0; end else if(en) begin dout_p0_r1 <= dout_p0_r0; dout_p1_r1 <= dout_p1_r0; dout_p2_r1 <= dout_p2_r0; dout_p3_r1 <= dout_p3_r0; dout_p4_r1 <= dout_p4_r0; dout_p5_r1 <= dout_p5_r0; dout_p6_r1 <= dout_p6_r0; dout_p7_r1 <= dout_p7_r0; end else begin dout_p0_r1 <= dout_p0_r1; dout_p1_r1 <= dout_p1_r1; dout_p2_r1 <= dout_p2_r1; dout_p3_r1 <= dout_p3_r1; dout_p4_r1 <= dout_p4_r1; dout_p5_r1 <= dout_p5_r1; dout_p6_r1 <= dout_p6_r1; dout_p7_r1 <= dout_p7_r1; end reg signed [18:0] dout_p0_r2; reg signed [18:0] dout_p0_r3; reg signed [18:0] dout_p0_r4; reg signed [18:0] dout_p0_r5; reg signed [18:0] dout_p0_r6; always @(posedge clk or negedge rstn) if (!rstn) begin dout_p0_r2 <= 16'd0; dout_p0_r3 <= 16'd0; dout_p0_r4 <= 16'd0; dout_p0_r5 <= 16'd0; dout_p0_r6 <= 16'd0; end else if(en) begin dout_p0_r2 <= dout_p0_r1; dout_p0_r3 <= dout_p0_r2; dout_p0_r4 <= dout_p0_r3; dout_p0_r5 <= dout_p0_r4; dout_p0_r6 <= dout_p0_r5; end else begin dout_p0_r2 <= dout_p0_r2; dout_p0_r3 <= dout_p0_r3; dout_p0_r4 <= dout_p0_r4; dout_p0_r5 <= dout_p0_r5; dout_p0_r6 <= dout_p0_r6; end reg vldo_diff_r1; reg vldo_diff_r2; reg vldo_diff_r3; reg vldo_diff_r4; reg vldo_diff_r5; reg vldo_diff_r6; reg vldo_diff_r7; reg vldo_diff_r8; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldo_diff_r1 <= 16'd0; vldo_diff_r2 <= 16'd0; vldo_diff_r3 <= 16'd0; vldo_diff_r4 <= 16'd0; vldo_diff_r5 <= 16'd0; vldo_diff_r6 <= 16'd0; vldo_diff_r7 <= 16'd0; vldo_diff_r8 <= 16'd0; end else if(en) begin vldo_diff_r1 <= vldo_diff; vldo_diff_r2 <= vldo_diff_r1; vldo_diff_r3 <= vldo_diff_r2; vldo_diff_r4 <= vldo_diff_r3; vldo_diff_r5 <= vldo_diff_r4; vldo_diff_r6 <= vldo_diff_r5; vldo_diff_r7 <= vldo_diff_r6; vldo_diff_r8 <= vldo_diff_r7; end else begin vldo_diff_r1 <= vldo_diff_r1; vldo_diff_r2 <= vldo_diff_r2; vldo_diff_r3 <= vldo_diff_r3; vldo_diff_r4 <= vldo_diff_r4; vldo_diff_r5 <= vldo_diff_r5; vldo_diff_r6 <= vldo_diff_r6; vldo_diff_r7 <= vldo_diff_r7; vldo_diff_r8 <= vldo_diff_r8; end end wire vldo_r0_h; wire vldo_r0_l; reg vldo_r0; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldo_r0 <= 0; end else if(vldo_r0_h)begin vldo_r0 <= 1; end else if(vldo_r0_l)begin vldo_r0 <= 0; end end assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0_r1 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); assign vldo_r0_h = vldo_diff_r8 == 0 && vldo_diff_r7 == 1 ; assign vldo = vldo_r0; endmodule