//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    Z_dsp_en_Test.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-11-04      thfu            Test Enable signal using clk divided by 2
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module 	z_dsp_en_Test	 	
(
		 	clk,

		 	rstn,
		 	dac_mode_sel, 	//2'b00:NRZ mode;2'b01:Double data mode;
                                        //2'b10:Double Double data mode;2'b11:reserve;
		 	tc_bypass, 	
		 	intp_mode, 	//2'b00:x1;2'b01:x2,'b10:x4;other:reserve;
		 	din_re,	
		 	din_im,	
			a0_re, 		//a0's real part
			a0_im,		//a0's image part
			b0_re,
			b0_im,
			a1_re,
			a1_im,
			b1_re,
			b1_im,
			a2_re,
			a2_im,
			b2_re,
			b2_im,
			a3_re,
			a3_im,
			b3_re,
			b3_im,
			a4_re,
			a4_im,
			b4_re,
			b4_im,
			a5_re,
			a5_im,
			b5_re,
			b5_im,
			dout0,
			dout1,	
			dout2,	
			dout3,		
			dout4,
			dout5,	
			dout6,	
			dout7,
                        vldo	
		 	);		

input  rstn;
input  clk;
input  tc_bypass;
input  [1:0]	intp_mode;
input  [1:0]	dac_mode_sel;
input  signed [15:0] din_re;
input  signed [15:0] din_im;
input  signed [36:0] a0_re;
input  signed [36:0] a0_im;
input  signed [20:0] b0_re;
input  signed [20:0] b0_im;
input  signed [36:0] a1_re;
input  signed [36:0] a1_im;
input  signed [20:0] b1_re;
input  signed [20:0] b1_im;
input  signed [36:0] a2_re;
input  signed [36:0] a2_im;
input  signed [20:0] b2_re;
input  signed [20:0] b2_im;
input  signed [36:0] a3_re;
input  signed [36:0] a3_im;
input  signed [20:0] b3_re;
input  signed [20:0] b3_im;
input  signed [36:0] a4_re;
input  signed [36:0] a4_im;
input  signed [20:0] b4_re;
input  signed [20:0] b4_im;
input  signed [36:0] a5_re;
input  signed [36:0] a5_im;
input  signed [20:0] b5_re;
input  signed [20:0] b5_im;

output signed [15:0] dout0;
output signed [15:0] dout1;
output signed [15:0] dout2;
output signed [15:0] dout3;
output signed [15:0] dout4;
output signed [15:0] dout5;
output signed [15:0] dout6;
output signed [15:0] dout7;
output		     vldo;

wire signed	[15:0] IIR_out;

reg  en;

always@(posedge clk or negedge rstn)
	if(!rstn)
		en  <= 0;
        else
		en  <= ~en;

reg	[13:0]		  vldo_r;

always@(posedge clk or negedge rstn)
	if(!rstn)
		begin
			vldo_r	<=	9'b0;			
		end
	else
		begin
			vldo_r	<=	{vldo_r[13:0], en};
		end

assign		vldo = vldo_r[13];

TailCorr_top	inst_TailCorr_top
               (
		        .clk			(clk	                ),
		        .rstn			(rstn			),
			.en			(en			),
			.tc_bypass		(tc_bypass		),
		        .din_re			(din_re                 ),
		        .din_im			(din_im                 ),
			.a0_re			(a0_re                  ),
			.a0_im			(a0_im                  ),
			.b0_re			(b0_re                  ),
			.b0_im			(b0_im                  ),
			.a1_re			(a1_re                  ),
			.a1_im			(a1_im                  ),
			.b1_re			(b1_re                  ),
			.b1_im			(b1_im                  ), 
			.a2_re			(a2_re                  ),
			.a2_im			(a2_im                  ),
			.b2_re			(b2_re                  ),
			.b2_im			(b2_im                  ),  
			.a3_re			(a3_re                  ),
			.a3_im			(a3_im                  ),
			.b3_re			(b3_re                  ),
			.b3_im			(b3_im                  ),
			.a4_re			(a4_re                  ),
			.a4_im			(a4_im                  ),
			.b4_re			(b4_re                  ),
			.b4_im			(b4_im                  ), 
			.a5_re			(a5_re                  ),
			.a5_im			(a5_im                  ),
			.b5_re			(b5_re                  ),
			.b5_im			(b5_im                  ),                         
		        .dout			(IIR_out                )
                );

wire signed	[15:0] dout_0;
wire signed	[15:0] dout_1;
wire signed	[15:0] dout_2;
wire signed	[15:0] dout_3;
wire signed	[15:0] dout_4;
wire signed	[15:0] dout_5;
wire signed	[15:0] dout_6;
wire signed	[15:0] dout_7;


MeanIntp_8		inst_MeanIntp_8
		       (
			.clk				(clk		        ),
			.rstn				(rstn			),
			.en				(en			),
			.intp_mode			(intp_mode		),
                        .din	                	(IIR_out		),           
			.dout_0				(dout_0        	        ),
			.dout_1				(dout_1          	),
			.dout_2				(dout_2          	),
			.dout_3				(dout_3           	),
			.dout_4				(dout_4        	        ),
			.dout_5				(dout_5          	),
			.dout_6				(dout_6          	),
			.dout_7				(dout_7           	)

		        );

lsdacif			inst_lsdacif
		       (
			.clk				(clk		        ),
			.rstn				(rstn			),
			.dac_mode_sel			(dac_mode_sel		),
			.intp_mode			(intp_mode		),
                        .din0	                	(dout_0			),  
                        .din1	                	(dout_1			),           
                        .din2	                	(dout_2			),           
                        .din3	                	(dout_3			),                    
                        .din4	                	(dout_4			),  
                        .din5	                	(dout_5			),           
                        .din6	                	(dout_6			),           
                        .din7	                	(dout_7			),
			.dout0				(dout0                  ),
			.dout1				(dout1                  ),
			.dout2				(dout2                  ),
			.dout3				(dout3                  ),
			.dout4				(dout4                  ),
			.dout5				(dout5                  ),
			.dout6				(dout6                  ),
			.dout7				(dout7                  )

		        );

endmodule