//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    mult_C.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-05-28      thfu
//2024-05-28 10:22:18 
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module mult_C(
            clk,
            rstn,
            en,
            a,
            b,
			c,
			d,
			Re,
			Im
);

parameter	integer A_width = 8;
parameter	integer B_width = 8;
parameter	integer C_width = 8;
parameter	integer D_width = 8;

input                                       rstn;
input                                       clk;
input                                       en;
input       signed  [A_width-1:0]           a;
input       signed  [B_width-1:0]           b;
input       signed  [C_width-1:0]           c;
input       signed  [D_width-1:0]           d;

output      signed  [A_width+C_width-22:0]  Re;
output      signed  [A_width+D_width-22:0]  Im;

wire	    signed	[A_width+C_width-1:0]	ac;
wire	    signed	[B_width+D_width-1:0]	bd;
wire	    signed	[A_width+D_width-1:0]	ad;
wire	    signed	[B_width+C_width-1:0]	bc;

reg         signed  [A_width+C_width:0]     Re_tmp;
reg         signed  [A_width+D_width:0]     Im_tmp;

DW02_mult	#(A_width,C_width) inst_c1(	.A		(a		),
						.B		(c		),
						.TC		(1'b1		),
						.PRODUCT	(ac		)
				);

DW02_mult	#(B_width,D_width) inst_c2(	.A		(b		),
						.B		(d		),
						.TC		(1'b1		),
						.PRODUCT	(bd		)
				);

DW02_mult	#(A_width,D_width) inst_c3(	.A		(a		),
						.B		(d		),
						.TC		(1'b1		),
						.PRODUCT	(ad		)
				);
DW02_mult	#(B_width,C_width) inst_c4(	.A		(b		),
						.B		(c		),
						.TC		(1'b1		),
						.PRODUCT	(bc		)
				);

always@(posedge clk or negedge rstn)
		if(!rstn)
			 begin
				Re_tmp  <=	'h0;
				Im_tmp	<=	'h0;
			 end 
		else if(en)
			 begin
				Re_tmp  <=	ac - bd;
				Im_tmp	<=	ad + bc;
			 end 
		else
			 begin
				Re_tmp  <=	Re_tmp;
				Im_tmp	<=	Im_tmp;
			 end 

assign	Re = Re_tmp[A_width+D_width-1:20];
assign	Im = Im_tmp[A_width+D_width-1:20];

endmodule