//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : TailCorr_top.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.3 2024-05-15 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module diff_p_ref ( input rstn ,input clk ,input en ,input vldi ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 ,output vldo ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 ,output signed [15:0] dout_p2 ,output signed [15:0] dout_p3 ,output signed [15:0] dout_p4 ,output signed [15:0] dout_p5 ,output signed [15:0] dout_p6 ,output signed [15:0] dout_p7 ,output signed [15:0] diff_p0 ,output signed [15:0] diff_p1 ,output signed [15:0] diff_p2 ,output signed [15:0] diff_p3 ,output signed [15:0] diff_p4 ,output signed [15:0] diff_p5 ,output signed [15:0] diff_p6 ,output signed [15:0] diff_p7 ); wire signed [15:0] din_p0_r0; wire signed [15:0] din_p1_r0; wire signed [15:0] din_p2_r0; wire signed [15:0] din_p3_r0; wire signed [15:0] din_p4_r0; wire signed [15:0] din_p5_r0; wire signed [15:0] din_p6_r0; wire signed [15:0] din_p7_r0; s2p_2_ref inst1_s2p_2_ref ( .clk (clk), .rst_n (rstn), .din (din0), .en (vldi), .dout0 (din_p0_r0), .dout1 (din_p4_r0) ,.vldo( vldo) ); s2p_2_ref inst2_s2p_2_ref ( .clk (clk), .rst_n (rstn), .din (din1), .en (vldi), .dout0 (din_p1_r0), .dout1 (din_p5_r0) ,.vldo( ) ); s2p_2_ref inst3_s2p_2_ref ( .clk (clk), .rst_n (rstn), .din (din2), .en (vldi), .dout0 (din_p2_r0), .dout1 (din_p6_r0) ,.vldo( ) ); s2p_2_ref inst4_s2p_2_ref ( .clk (clk), .rst_n (rstn), .din (din3), .en (vldi), .dout0 (din_p3_r0), .dout1 (din_p7_r0) ,.vldo( ) ); reg signed [15:0] din_p0_r1; reg signed [15:0] din_p1_r1; reg signed [15:0] din_p2_r1; reg signed [15:0] din_p3_r1; reg signed [15:0] din_p4_r1; reg signed [15:0] din_p5_r1; reg signed [15:0] din_p6_r1; reg signed [15:0] din_p7_r1; always @(posedge clk or negedge rstn) if (!rstn) begin din_p0_r1 <= 'h0; din_p1_r1 <= 'h0; din_p2_r1 <= 'h0; din_p3_r1 <= 'h0; din_p4_r1 <= 'h0; din_p5_r1 <= 'h0; din_p6_r1 <= 'h0; din_p7_r1 <= 'h0; end else if(en) begin din_p0_r1 <= din_p0_r0; din_p1_r1 <= din_p1_r0; din_p2_r1 <= din_p2_r0; din_p3_r1 <= din_p3_r0; din_p4_r1 <= din_p4_r0; din_p5_r1 <= din_p5_r0; din_p6_r1 <= din_p6_r0; din_p7_r1 <= din_p7_r0; end else begin din_p0_r1 <= din_p0_r1; din_p1_r1 <= din_p1_r1; din_p2_r1 <= din_p2_r1; din_p3_r1 <= din_p3_r1; din_p4_r1 <= din_p4_r1; din_p5_r1 <= din_p5_r1; din_p6_r1 <= din_p6_r1; din_p7_r1 <= din_p7_r1; end assign dout_p0 = din_p0_r1; assign dout_p1 = din_p1_r1; assign dout_p2 = din_p2_r1; assign dout_p3 = din_p3_r1; assign dout_p4 = din_p4_r1; assign dout_p5 = din_p5_r1; assign dout_p6 = din_p6_r1; assign dout_p7 = din_p7_r1; wire signed [15:0] diff_p0_r0; wire signed [15:0] diff_p1_r0; wire signed [15:0] diff_p2_r0; wire signed [15:0] diff_p3_r0; wire signed [15:0] diff_p4_r0; wire signed [15:0] diff_p5_r0; wire signed [15:0] diff_p6_r0; wire signed [15:0] diff_p7_r0; assign diff_p0_r0 = din_p0_r0 - din_p7_r1; assign diff_p1_r0 = din_p1_r0 - din_p0_r0; assign diff_p2_r0 = din_p2_r0 - din_p1_r0; assign diff_p3_r0 = din_p3_r0 - din_p2_r0; assign diff_p4_r0 = din_p4_r0 - din_p3_r0; assign diff_p5_r0 = din_p5_r0 - din_p4_r0; assign diff_p6_r0 = din_p6_r0 - din_p5_r0; assign diff_p7_r0 = din_p7_r0 - din_p6_r0; reg signed [15:0] diff_p0_r1; reg signed [15:0] diff_p1_r1; reg signed [15:0] diff_p2_r1; reg signed [15:0] diff_p3_r1; reg signed [15:0] diff_p4_r1; reg signed [15:0] diff_p5_r1; reg signed [15:0] diff_p6_r1; reg signed [15:0] diff_p7_r1; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin diff_p0_r1 <= 0; diff_p1_r1 <= 0; diff_p2_r1 <= 0; diff_p3_r1 <= 0; diff_p4_r1 <= 0; diff_p5_r1 <= 0; diff_p6_r1 <= 0; diff_p7_r1 <= 0; end else if(en)begin diff_p0_r1 <= diff_p0_r0; diff_p1_r1 <= diff_p1_r0; diff_p2_r1 <= diff_p2_r0; diff_p3_r1 <= diff_p3_r0; diff_p4_r1 <= diff_p4_r0; diff_p5_r1 <= diff_p5_r0; diff_p6_r1 <= diff_p6_r0; diff_p7_r1 <= diff_p7_r0; end else begin diff_p0_r1 <= diff_p0_r1; diff_p1_r1 <= diff_p1_r1; diff_p2_r1 <= diff_p2_r1; diff_p3_r1 <= diff_p3_r1; diff_p4_r1 <= diff_p4_r1; diff_p5_r1 <= diff_p5_r1; diff_p6_r1 <= diff_p6_r1; diff_p7_r1 <= diff_p7_r1; end end assign diff_p0 = diff_p0_r1; assign diff_p1 = diff_p1_r1; assign diff_p2 = diff_p2_r1; assign diff_p3 = diff_p3_r1; assign diff_p4 = diff_p4_r1; assign diff_p5 = diff_p5_r1; assign diff_p6 = diff_p6_r1; assign diff_p7 = diff_p7_r1; endmodule