//+FHDR-------------------------------------------------------------------------------------------------------- // Company: //----------------------------------------------------------------------------------------------------------------- // File Name : TailCorr_top.v // Department : // Author : thfu // Author's Tel : //----------------------------------------------------------------------------------------------------------------- // Relese History // Version Date Author Description // 0.3 2025-02-28 thfu //----------------------------------------------------------------------------------------------------------------- // Keywords : // //----------------------------------------------------------------------------------------------------------------- // Parameter // //----------------------------------------------------------------------------------------------------------------- // Purpose : // //----------------------------------------------------------------------------------------------------------------- // Target Device: // Tool versions: //----------------------------------------------------------------------------------------------------------------- // Reuse Issues // Reset Strategy: // Clock Domains: // Critical Timing: // Asynchronous I/F: // Synthesizable (y/n): // Other: //-FHDR-------------------------------------------------------------------------------------------------------- module TailCorr_top #( parameter temp_var_width = 23 ) ( input rstn ,input clk ,input en ,input vldi ,input signed [15:0] din0 ,input signed [15:0] din1 ,input signed [15:0] din2 ,input signed [15:0] din3 ,input signed [31:0] a_re0 ,input signed [31:0] a_im0 ,input signed [31:0] b_re0 ,input signed [31:0] b_im0 ,input signed [31:0] ab_re0 ,input signed [31:0] ab_im0 ,input signed [31:0] abb_re0 ,input signed [31:0] abb_im0 ,input signed [31:0] ab_pow3_re0 ,input signed [31:0] ab_pow3_im0 ,input signed [31:0] ab_pow4_re0 ,input signed [31:0] ab_pow4_im0 ,input signed [31:0] ab_pow5_re0 ,input signed [31:0] ab_pow5_im0 ,input signed [31:0] ab_pow6_re0 ,input signed [31:0] ab_pow6_im0 ,input signed [31:0] ab_pow7_re0 ,input signed [31:0] ab_pow7_im0 ,input signed [31:0] b_pow8_re0 ,input signed [31:0] b_pow8_im0 ,input signed [31:0] a_re1 ,input signed [31:0] a_im1 ,input signed [31:0] b_re1 ,input signed [31:0] b_im1 ,input signed [31:0] ab_re1 ,input signed [31:0] ab_im1 ,input signed [31:0] abb_re1 ,input signed [31:0] abb_im1 ,input signed [31:0] ab_pow3_re1 ,input signed [31:0] ab_pow3_im1 ,input signed [31:0] ab_pow4_re1 ,input signed [31:0] ab_pow4_im1 ,input signed [31:0] ab_pow5_re1 ,input signed [31:0] ab_pow5_im1 ,input signed [31:0] ab_pow6_re1 ,input signed [31:0] ab_pow6_im1 ,input signed [31:0] ab_pow7_re1 ,input signed [31:0] ab_pow7_im1 ,input signed [31:0] b_pow8_re1 ,input signed [31:0] b_pow8_im1 ,input signed [31:0] a_re2 ,input signed [31:0] a_im2 ,input signed [31:0] b_re2 ,input signed [31:0] b_im2 ,input signed [31:0] ab_re2 ,input signed [31:0] ab_im2 ,input signed [31:0] abb_re2 ,input signed [31:0] abb_im2 ,input signed [31:0] ab_pow3_re2 ,input signed [31:0] ab_pow3_im2 ,input signed [31:0] ab_pow4_re2 ,input signed [31:0] ab_pow4_im2 ,input signed [31:0] ab_pow5_re2 ,input signed [31:0] ab_pow5_im2 ,input signed [31:0] ab_pow6_re2 ,input signed [31:0] ab_pow6_im2 ,input signed [31:0] ab_pow7_re2 ,input signed [31:0] ab_pow7_im2 ,input signed [31:0] b_pow8_re2 ,input signed [31:0] b_pow8_im2 ,input signed [31:0] a_re3 ,input signed [31:0] a_im3 ,input signed [31:0] b_re3 ,input signed [31:0] b_im3 ,input signed [31:0] ab_re3 ,input signed [31:0] ab_im3 ,input signed [31:0] abb_re3 ,input signed [31:0] abb_im3 ,input signed [31:0] ab_pow3_re3 ,input signed [31:0] ab_pow3_im3 ,input signed [31:0] ab_pow4_re3 ,input signed [31:0] ab_pow4_im3 ,input signed [31:0] ab_pow5_re3 ,input signed [31:0] ab_pow5_im3 ,input signed [31:0] ab_pow6_re3 ,input signed [31:0] ab_pow6_im3 ,input signed [31:0] ab_pow7_re3 ,input signed [31:0] ab_pow7_im3 ,input signed [31:0] b_pow8_re3 ,input signed [31:0] b_pow8_im3 ,input signed [31:0] a_re4 ,input signed [31:0] a_im4 ,input signed [31:0] b_re4 ,input signed [31:0] b_im4 ,input signed [31:0] ab_re4 ,input signed [31:0] ab_im4 ,input signed [31:0] abb_re4 ,input signed [31:0] abb_im4 ,input signed [31:0] ab_pow3_re4 ,input signed [31:0] ab_pow3_im4 ,input signed [31:0] ab_pow4_re4 ,input signed [31:0] ab_pow4_im4 ,input signed [31:0] ab_pow5_re4 ,input signed [31:0] ab_pow5_im4 ,input signed [31:0] ab_pow6_re4 ,input signed [31:0] ab_pow6_im4 ,input signed [31:0] ab_pow7_re4 ,input signed [31:0] ab_pow7_im4 ,input signed [31:0] b_pow8_re4 ,input signed [31:0] b_pow8_im4 ,input signed [31:0] a_re5 ,input signed [31:0] a_im5 ,input signed [31:0] b_re5 ,input signed [31:0] b_im5 ,input signed [31:0] ab_re5 ,input signed [31:0] ab_im5 ,input signed [31:0] abb_re5 ,input signed [31:0] abb_im5 ,input signed [31:0] ab_pow3_re5 ,input signed [31:0] ab_pow3_im5 ,input signed [31:0] ab_pow4_re5 ,input signed [31:0] ab_pow4_im5 ,input signed [31:0] ab_pow5_re5 ,input signed [31:0] ab_pow5_im5 ,input signed [31:0] ab_pow6_re5 ,input signed [31:0] ab_pow6_im5 ,input signed [31:0] ab_pow7_re5 ,input signed [31:0] ab_pow7_im5 ,input signed [31:0] b_pow8_re5 ,input signed [31:0] b_pow8_im5 ,output signed [15:0] dout_p0 ,output signed [15:0] dout_p1 ,output signed [15:0] dout_p2 ,output signed [15:0] dout_p3 ,output signed [15:0] dout_p4 ,output signed [15:0] dout_p5 ,output signed [15:0] dout_p6 ,output signed [15:0] dout_p7 ,output vldo ); wire signed [15:0] din_p0; wire signed [15:0] din_p1; wire signed [15:0] din_p2; wire signed [15:0] din_p3; wire signed [15:0] din_p4; wire signed [15:0] din_p5; wire signed [15:0] din_p6; wire signed [15:0] din_p7; wire signed [15:0] IIRin_p0; // iirin_x(8n+9) wire signed [15:0] IIRin_p1; // iirin_x(8n+10) wire signed [15:0] IIRin_p2; // iirin_x(8n+11) wire signed [15:0] IIRin_p3; // iirin_x(8n+12) wire signed [15:0] IIRin_p4; // iirin_x(8n+13) wire signed [15:0] IIRin_p5; // iirin_x(8n+14) wire signed [15:0] IIRin_p6; // iirin_x(8n+15) wire signed [15:0] IIRin_p7; // iirin_x(8n+16) wire signed [temp_var_width-1:0] IIRout_p0 [5:0]; // iirout_y(8n-8) wire signed [temp_var_width-1:0] IIRout_p1 [5:0]; // iirout_y(8n-23) wire signed [temp_var_width-1:0] IIRout_p2 [5:0]; // iirout_y(8n-38) wire signed [temp_var_width-1:0] IIRout_p3 [5:0]; // iirout_y(8n-53) wire signed [temp_var_width-1:0] IIRout_p4 [5:0]; // iirout_y(8n-68) wire signed [temp_var_width-1:0] IIRout_p5 [5:0]; // iirout_y(8n-83) wire signed [temp_var_width-1:0] IIRout_p6 [5:0]; // iirout_y(8n-98) wire signed [temp_var_width-1:0] IIRout_p7 [5:0]; // iirout_y(8n-113) wire signed [temp_var_width+2:0] sum_IIRout_p0; wire signed [temp_var_width+2:0] sum_IIRout_p1; wire signed [temp_var_width+2:0] sum_IIRout_p2; wire signed [temp_var_width+2:0] sum_IIRout_p3; wire signed [temp_var_width+2:0] sum_IIRout_p4; wire signed [temp_var_width+2:0] sum_IIRout_p5; wire signed [temp_var_width+2:0] sum_IIRout_p6; wire signed [temp_var_width+2:0] sum_IIRout_p7; reg signed [15:0] din_p0_r [15:0]; reg signed [15:0] din_p1_r [15:0]; reg signed [15:0] din_p2_r [15:0]; reg signed [15:0] din_p3_r [15:0]; reg signed [15:0] din_p4_r [15:0]; reg signed [15:0] din_p5_r [15:0]; reg signed [15:0] din_p6_r [15:0]; reg signed [15:0] din_p7_r [15:0]; reg signed [15:0] IIRin_p0_r [1 :0]; // iirin_x(8n-7) reg signed [15:0] IIRin_p1_r [3 :0]; // iirin_x(8n-22) reg signed [15:0] IIRin_p2_r [5 :0]; // iirin_x(8n-37) reg signed [15:0] IIRin_p3_r [7 :0]; // iirin_x(8n-53) reg signed [15:0] IIRin_p4_r [9 :0]; // iirin_x(8n-67) reg signed [15:0] IIRin_p5_r [11:0]; // iirin_x(8n-82) reg signed [15:0] IIRin_p6_r [13:0]; // iirin_x(8n-97) reg signed [temp_var_width+2:0] sum_IIRout_p0_r [12:0]; reg signed [temp_var_width+2:0] sum_IIRout_p1_r [11:0]; reg signed [temp_var_width+2:0] sum_IIRout_p2_r [9 :0]; reg signed [temp_var_width+2:0] sum_IIRout_p3_r [7 :0]; reg signed [temp_var_width+2:0] sum_IIRout_p4_r [5 :0]; reg signed [temp_var_width+2:0] sum_IIRout_p5_r [3 :0]; reg signed [temp_var_width+2:0] sum_IIRout_p6_r [1 :0]; wire signed [temp_var_width+2:0] dout_p0_r0; wire signed [temp_var_width+2:0] dout_p1_r0; wire signed [temp_var_width+2:0] dout_p2_r0; wire signed [temp_var_width+2:0] dout_p3_r0; wire signed [temp_var_width+2:0] dout_p4_r0; wire signed [temp_var_width+2:0] dout_p5_r0; wire signed [temp_var_width+2:0] dout_p6_r0; wire signed [temp_var_width+2:0] dout_p7_r0; wire vldo_diff; diff_p inst_diff_p ( .rstn (rstn), .clk (clk ), .en (en ), .vldi (vldi), .din0 (din0), .din1 (din1), .din2 (din2), .din3 (din3), .vldo (vldo_diff), .dout_p0 (din_p0), .dout_p1 (din_p1), .dout_p2 (din_p2), .dout_p3 (din_p3), .dout_p4 (din_p4), .dout_p5 (din_p5), .dout_p6 (din_p6), .dout_p7 (din_p7), .diff_p0 (IIRin_p0), .diff_p1 (IIRin_p1), .diff_p2 (IIRin_p2), .diff_p3 (IIRin_p3), .diff_p4 (IIRin_p4), .diff_p5 (IIRin_p5), .diff_p6 (IIRin_p6), .diff_p7 (IIRin_p7) ); integer i; always @(posedge clk or negedge rstn) begin if (!rstn) begin for (i = 0; i < 17; i = i + 1) begin din_p0_r[i] <= 'h0; din_p1_r[i] <= 'h0; din_p2_r[i] <= 'h0; din_p3_r[i] <= 'h0; din_p4_r[i] <= 'h0; din_p5_r[i] <= 'h0; din_p6_r[i] <= 'h0; din_p7_r[i] <= 'h0; end end else if (en) begin din_p0_r[0] <= din_p0; din_p1_r[0] <= din_p1; din_p2_r[0] <= din_p2; din_p3_r[0] <= din_p3; din_p4_r[0] <= din_p4; din_p5_r[0] <= din_p5; din_p6_r[0] <= din_p6; din_p7_r[0] <= din_p7; for (i = 0; i < 15; i = i + 1) begin din_p0_r[i+1] <= din_p0_r[i]; din_p1_r[i+1] <= din_p1_r[i]; din_p2_r[i+1] <= din_p2_r[i]; din_p3_r[i+1] <= din_p3_r[i]; din_p4_r[i+1] <= din_p4_r[i]; din_p5_r[i+1] <= din_p5_r[i]; din_p6_r[i+1] <= din_p6_r[i]; din_p7_r[i+1] <= din_p7_r[i]; end end end always @(posedge clk or negedge rstn) begin if (!rstn) begin for (i = 0; i < 2; i = i + 1) begin IIRin_p0_r[i] <= 'h0; end for (i = 0; i < 4; i = i + 1) begin IIRin_p1_r[i] <= 'h0; end for (i = 0; i < 6; i = i + 1) begin IIRin_p2_r[i] <= 'h0; end for (i = 0; i < 8; i = i + 1) begin IIRin_p3_r[i] <= 'h0; end for (i = 0; i <10; i = i + 1) begin IIRin_p4_r[i] <= 'h0; end for (i = 0; i <12; i = i + 1) begin IIRin_p5_r[i] <= 'h0; end for (i = 0; i <14; i = i + 1) begin IIRin_p6_r[i] <= 'h0; end end else if (en) begin IIRin_p0_r[0] <= IIRin_p0; IIRin_p1_r[0] <= IIRin_p1; IIRin_p2_r[0] <= IIRin_p2; IIRin_p3_r[0] <= IIRin_p3; IIRin_p4_r[0] <= IIRin_p4; IIRin_p5_r[0] <= IIRin_p5; IIRin_p6_r[0] <= IIRin_p6; for (i = 0; i < 1; i = i + 1) begin IIRin_p0_r[i+1] <= IIRin_p0_r[i]; end for (i = 0; i < 3; i = i + 1) begin IIRin_p1_r[i+1] <= IIRin_p1_r[i]; end for (i = 0; i < 5; i = i + 1) begin IIRin_p2_r[i+1] <= IIRin_p2_r[i]; end for (i = 0; i < 7; i = i + 1) begin IIRin_p3_r[i+1] <= IIRin_p3_r[i]; end for (i = 0; i < 9; i = i + 1) begin IIRin_p4_r[i+1] <= IIRin_p4_r[i]; end for (i = 0; i <11; i = i + 1) begin IIRin_p5_r[i+1] <= IIRin_p5_r[i]; end for (i = 0; i <13; i = i + 1) begin IIRin_p6_r[i+1] <= IIRin_p6_r[i]; end end end IIR_top inst_iir_top_0 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re0 ), .a_im (a_im0 ), .b_re (b_re0 ), .b_im (b_im0 ), .ab_re (ab_re0 ), .ab_im (ab_im0 ), .abb_re (abb_re0 ), .abb_im (abb_im0 ), .ab_pow3_re (ab_pow3_re0 ), .ab_pow3_im (ab_pow3_im0 ), .ab_pow4_re (ab_pow4_re0 ), .ab_pow4_im (ab_pow4_im0 ), .ab_pow5_re (ab_pow5_re0 ), .ab_pow5_im (ab_pow5_im0 ), .ab_pow6_re (ab_pow6_re0 ), .ab_pow6_im (ab_pow6_im0 ), .ab_pow7_re (ab_pow7_re0 ), .ab_pow7_im (ab_pow7_im0 ), .b_pow8_re (b_pow8_re0 ), .b_pow8_im (b_pow8_im0 ), .IIRout_p0 (IIRout_p0[0] ), .IIRout_p1 (IIRout_p1[0] ), .IIRout_p2 (IIRout_p2[0] ), .IIRout_p3 (IIRout_p3[0] ), .IIRout_p4 (IIRout_p4[0] ), .IIRout_p5 (IIRout_p5[0] ), .IIRout_p6 (IIRout_p6[0] ), .IIRout_p7 (IIRout_p7[0] ) ); IIR_top inst_iir_top_1 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re1 ), .a_im (a_im1 ), .b_re (b_re1 ), .b_im (b_im1 ), .ab_re (ab_re1 ), .ab_im (ab_im1 ), .abb_re (abb_re1 ), .abb_im (abb_im1 ), .ab_pow3_re (ab_pow3_re1 ), .ab_pow3_im (ab_pow3_im1 ), .ab_pow4_re (ab_pow4_re1 ), .ab_pow4_im (ab_pow4_im1 ), .ab_pow5_re (ab_pow5_re1 ), .ab_pow5_im (ab_pow5_im1 ), .ab_pow6_re (ab_pow6_re1 ), .ab_pow6_im (ab_pow6_im1 ), .ab_pow7_re (ab_pow7_re1 ), .ab_pow7_im (ab_pow7_im1 ), .b_pow8_re (b_pow8_re1 ), .b_pow8_im (b_pow8_im1 ), .IIRout_p0 (IIRout_p0[1] ), .IIRout_p1 (IIRout_p1[1] ), .IIRout_p2 (IIRout_p2[1] ), .IIRout_p3 (IIRout_p3[1] ), .IIRout_p4 (IIRout_p4[1] ), .IIRout_p5 (IIRout_p5[1] ), .IIRout_p6 (IIRout_p6[1] ), .IIRout_p7 (IIRout_p7[1] ) ); IIR_top inst_iir_top_2 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re2 ), .a_im (a_im2 ), .b_re (b_re2 ), .b_im (b_im2 ), .ab_re (ab_re2 ), .ab_im (ab_im2 ), .abb_re (abb_re2 ), .abb_im (abb_im2 ), .ab_pow3_re (ab_pow3_re2 ), .ab_pow3_im (ab_pow3_im2 ), .ab_pow4_re (ab_pow4_re2 ), .ab_pow4_im (ab_pow4_im2 ), .ab_pow5_re (ab_pow5_re2 ), .ab_pow5_im (ab_pow5_im2 ), .ab_pow6_re (ab_pow6_re2 ), .ab_pow6_im (ab_pow6_im2 ), .ab_pow7_re (ab_pow7_re2 ), .ab_pow7_im (ab_pow7_im2 ), .b_pow8_re (b_pow8_re2 ), .b_pow8_im (b_pow8_im2 ), .IIRout_p0 (IIRout_p0[2] ), .IIRout_p1 (IIRout_p1[2] ), .IIRout_p2 (IIRout_p2[2] ), .IIRout_p3 (IIRout_p3[2] ), .IIRout_p4 (IIRout_p4[2] ), .IIRout_p5 (IIRout_p5[2] ), .IIRout_p6 (IIRout_p6[2] ), .IIRout_p7 (IIRout_p7[2] ) ); IIR_top inst_iir_top_3 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re3 ), .a_im (a_im3 ), .b_re (b_re3 ), .b_im (b_im3 ), .ab_re (ab_re3 ), .ab_im (ab_im3 ), .abb_re (abb_re3 ), .abb_im (abb_im3 ), .ab_pow3_re (ab_pow3_re3 ), .ab_pow3_im (ab_pow3_im3 ), .ab_pow4_re (ab_pow4_re3 ), .ab_pow4_im (ab_pow4_im3 ), .ab_pow5_re (ab_pow5_re3 ), .ab_pow5_im (ab_pow5_im3 ), .ab_pow6_re (ab_pow6_re3 ), .ab_pow6_im (ab_pow6_im3 ), .ab_pow7_re (ab_pow7_re3 ), .ab_pow7_im (ab_pow7_im3 ), .b_pow8_re (b_pow8_re3 ), .b_pow8_im (b_pow8_im3 ), .IIRout_p0 (IIRout_p0[3] ), .IIRout_p1 (IIRout_p1[3] ), .IIRout_p2 (IIRout_p2[3] ), .IIRout_p3 (IIRout_p3[3] ), .IIRout_p4 (IIRout_p4[3] ), .IIRout_p5 (IIRout_p5[3] ), .IIRout_p6 (IIRout_p6[3] ), .IIRout_p7 (IIRout_p7[3] ) ); IIR_top inst_iir_top_4 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re4 ), .a_im (a_im4 ), .b_re (b_re4 ), .b_im (b_im4 ), .ab_re (ab_re4 ), .ab_im (ab_im4 ), .abb_re (abb_re4 ), .abb_im (abb_im4 ), .ab_pow3_re (ab_pow3_re4 ), .ab_pow3_im (ab_pow3_im4 ), .ab_pow4_re (ab_pow4_re4 ), .ab_pow4_im (ab_pow4_im4 ), .ab_pow5_re (ab_pow5_re4 ), .ab_pow5_im (ab_pow5_im4 ), .ab_pow6_re (ab_pow6_re4 ), .ab_pow6_im (ab_pow6_im4 ), .ab_pow7_re (ab_pow7_re4 ), .ab_pow7_im (ab_pow7_im4 ), .b_pow8_re (b_pow8_re4 ), .b_pow8_im (b_pow8_im4 ), .IIRout_p0 (IIRout_p0[4] ), .IIRout_p1 (IIRout_p1[4] ), .IIRout_p2 (IIRout_p2[4] ), .IIRout_p3 (IIRout_p3[4] ), .IIRout_p4 (IIRout_p4[4] ), .IIRout_p5 (IIRout_p5[4] ), .IIRout_p6 (IIRout_p6[4] ), .IIRout_p7 (IIRout_p7[4] ) ); IIR_top inst_iir_top_5 ( .clk (clk ), .rstn (rstn ), .en (en ), .IIRin_p0 (IIRin_p0 ), .IIRin_p1 (IIRin_p1 ), .IIRin_p2 (IIRin_p2 ), .IIRin_p3 (IIRin_p3 ), .IIRin_p4 (IIRin_p4 ), .IIRin_p5 (IIRin_p5 ), .IIRin_p6 (IIRin_p6 ), .IIRin_p7 (IIRin_p7 ), .IIRin_p0_r2 (IIRin_p0_r[1]), .IIRin_p1_r4 (IIRin_p1_r[3]), .IIRin_p2_r6 (IIRin_p2_r[5]), .IIRin_p3_r8 (IIRin_p3_r[7]), .IIRin_p4_r10 (IIRin_p4_r[9]), .IIRin_p5_r12 (IIRin_p5_r[11]), .IIRin_p6_r14 (IIRin_p6_r[13]), .a_re (a_re5 ), .a_im (a_im5 ), .b_re (b_re5 ), .b_im (b_im5 ), .ab_re (ab_re5 ), .ab_im (ab_im5 ), .abb_re (abb_re5 ), .abb_im (abb_im5 ), .ab_pow3_re (ab_pow3_re5 ), .ab_pow3_im (ab_pow3_im5 ), .ab_pow4_re (ab_pow4_re5 ), .ab_pow4_im (ab_pow4_im5 ), .ab_pow5_re (ab_pow5_re5 ), .ab_pow5_im (ab_pow5_im5 ), .ab_pow6_re (ab_pow6_re5 ), .ab_pow6_im (ab_pow6_im5 ), .ab_pow7_re (ab_pow7_re5 ), .ab_pow7_im (ab_pow7_im5 ), .b_pow8_re (b_pow8_re5 ), .b_pow8_im (b_pow8_im5 ), .IIRout_p0 (IIRout_p0[5] ), .IIRout_p1 (IIRout_p1[5] ), .IIRout_p2 (IIRout_p2[5] ), .IIRout_p3 (IIRout_p3[5] ), .IIRout_p4 (IIRout_p4[5] ), .IIRout_p5 (IIRout_p5[5] ), .IIRout_p6 (IIRout_p6[5] ), .IIRout_p7 (IIRout_p7[5] ) ); assign sum_IIRout_p0 = IIRout_p0[0] + IIRout_p0[1] +IIRout_p0[2] +IIRout_p0[3] +IIRout_p0[4] +IIRout_p0[5]; assign sum_IIRout_p1 = IIRout_p1[0] + IIRout_p1[1] +IIRout_p1[2] +IIRout_p1[3] +IIRout_p1[4] +IIRout_p1[5]; assign sum_IIRout_p2 = IIRout_p2[0] + IIRout_p2[1] +IIRout_p2[2] +IIRout_p2[3] +IIRout_p2[4] +IIRout_p2[5]; assign sum_IIRout_p3 = IIRout_p3[0] + IIRout_p3[1] +IIRout_p3[2] +IIRout_p3[3] +IIRout_p3[4] +IIRout_p3[5]; assign sum_IIRout_p4 = IIRout_p4[0] + IIRout_p4[1] +IIRout_p4[2] +IIRout_p4[3] +IIRout_p4[4] +IIRout_p4[5]; assign sum_IIRout_p5 = IIRout_p5[0] + IIRout_p5[1] +IIRout_p5[2] +IIRout_p5[3] +IIRout_p5[4] +IIRout_p5[5]; assign sum_IIRout_p6 = IIRout_p6[0] + IIRout_p6[1] +IIRout_p6[2] +IIRout_p6[3] +IIRout_p6[4] +IIRout_p6[5]; assign sum_IIRout_p7 = IIRout_p7[0] + IIRout_p7[1] +IIRout_p7[2] +IIRout_p7[3] +IIRout_p7[4] +IIRout_p7[5]; /*trunc #(20, 19, 3) round_u0 (clk, rstn, en, sum_IIRout_p0, sum_IIRout_p0_trunc); trunc #(20, 19, 3) round_u1 (clk, rstn, en, sum_IIRout_p1, sum_IIRout_p1_trunc); trunc #(20, 19, 3) round_u2 (clk, rstn, en, sum_IIRout_p2, sum_IIRout_p2_trunc); trunc #(20, 19, 3) round_u3 (clk, rstn, en, sum_IIRout_p3, sum_IIRout_p3_trunc); trunc #(20, 19, 3) round_u4 (clk, rstn, en, sum_IIRout_p4, sum_IIRout_p4_trunc); trunc #(20, 19, 3) round_u5 (clk, rstn, en, sum_IIRout_p5, sum_IIRout_p5_trunc); trunc #(20, 19, 3) round_u6 (clk, rstn, en, sum_IIRout_p6, sum_IIRout_p6_trunc); trunc #(20, 19, 3) round_u7 (clk, rstn, en, sum_IIRout_p7, sum_IIRout_p7_trunc);*/ always @(posedge clk or negedge rstn) begin if (!rstn) begin for (i = 0; i < 2; i = i + 1) begin sum_IIRout_p6_r[i] <= 'h0; end for (i = 0; i < 4; i = i + 1) begin sum_IIRout_p5_r[i] <= 'h0; end for (i = 0; i < 6; i = i + 1) begin sum_IIRout_p4_r[i] <= 'h0; end for (i = 0; i < 8; i = i + 1) begin sum_IIRout_p3_r[i] <= 'h0; end for (i = 0; i <10; i = i + 1) begin sum_IIRout_p2_r[i] <= 'h0; end for (i = 0; i <12; i = i + 1) begin sum_IIRout_p1_r[i] <= 'h0; end for (i = 0; i <13; i = i + 1) begin sum_IIRout_p0_r[i] <= 'h0; end end else if (en) begin sum_IIRout_p6_r[0] <= sum_IIRout_p6; sum_IIRout_p5_r[0] <= sum_IIRout_p5; sum_IIRout_p4_r[0] <= sum_IIRout_p4; sum_IIRout_p3_r[0] <= sum_IIRout_p3; sum_IIRout_p2_r[0] <= sum_IIRout_p2; sum_IIRout_p1_r[0] <= sum_IIRout_p1; sum_IIRout_p0_r[0] <= sum_IIRout_p0; for (i = 0; i < 1; i = i + 1) begin sum_IIRout_p6_r[i+1] <= sum_IIRout_p6_r[i]; end for (i = 0; i < 3; i = i + 1) begin sum_IIRout_p5_r[i+1] <= sum_IIRout_p5_r[i]; end for (i = 0; i < 5; i = i + 1) begin sum_IIRout_p4_r[i+1] <= sum_IIRout_p4_r[i]; end for (i = 0; i < 7; i = i + 1) begin sum_IIRout_p3_r[i+1] <= sum_IIRout_p3_r[i]; end for (i = 0; i < 9; i = i + 1) begin sum_IIRout_p2_r[i+1] <= sum_IIRout_p2_r[i]; end for (i = 0; i <11; i = i + 1) begin sum_IIRout_p1_r[i+1] <= sum_IIRout_p1_r[i]; end for (i = 0; i <12; i = i + 1) begin sum_IIRout_p0_r[i+1] <= sum_IIRout_p0_r[i]; end end end assign dout_p0_r0 = {{3{din_p0_r[15][15]}},din_p0_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p1_r[11]; // y(8n-119) assign dout_p1_r0 = {{3{din_p1_r[15][15]}},din_p1_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p2_r[9]; // y(8n-118) assign dout_p2_r0 = {{3{din_p2_r[15][15]}},din_p2_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p3_r[7]; // y(8n-117) assign dout_p3_r0 = {{3{din_p3_r[15][15]}},din_p3_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p4_r[5]; // y(8n-116) assign dout_p4_r0 = {{3{din_p4_r[15][15]}},din_p4_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p5_r[3]; // y(8n-115) assign dout_p5_r0 = {{3{din_p5_r[15][15]}},din_p5_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p6_r[1]; // y(8n-114) assign dout_p6_r0 = {{3{din_p6_r[15][15]}},din_p6_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p7; // y(8n-113) assign dout_p7_r0 = {{3{din_p7_r[15][15]}},din_p7_r[15],{(temp_var_width-16){1'b0}}} + sum_IIRout_p0_r[12]; // y(8n-112) trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u0 (clk, rstn, en, dout_p0_r0, dout_p0); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u1 (clk, rstn, en, dout_p1_r0, dout_p1); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u2 (clk, rstn, en, dout_p2_r0, dout_p2); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u3 (clk, rstn, en, dout_p3_r0, dout_p3); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u4 (clk, rstn, en, dout_p4_r0, dout_p4); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u5 (clk, rstn, en, dout_p5_r0, dout_p5); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u6 (clk, rstn, en, dout_p6_r0, dout_p6); trunc #(temp_var_width+3,temp_var_width-1,temp_var_width-16,1) round_u7 (clk, rstn, en, dout_p7_r0, dout_p7); // reg signed [15:0] dout_p0_r2; reg signed [15:0] dout_p0_r3; reg signed [15:0] dout_p0_r4; reg signed [15:0] dout_p0_r5; reg signed [15:0] dout_p0_r6; always @(posedge clk or negedge rstn) if (!rstn) begin dout_p0_r2 <= 16'd0; dout_p0_r3 <= 16'd0; dout_p0_r4 <= 16'd0; dout_p0_r5 <= 16'd0; dout_p0_r6 <= 16'd0; end else if(en) begin dout_p0_r2 <= dout_p0; dout_p0_r3 <= dout_p0_r2; dout_p0_r4 <= dout_p0_r3; dout_p0_r5 <= dout_p0_r4; dout_p0_r6 <= dout_p0_r5; end else begin dout_p0_r2 <= dout_p0_r2; dout_p0_r3 <= dout_p0_r3; dout_p0_r4 <= dout_p0_r4; dout_p0_r5 <= dout_p0_r5; dout_p0_r6 <= dout_p0_r6; end reg [18:0] vldo_diff_r; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldo_diff_r <= 19'b0; end else if(en) begin vldo_diff_r[0] <= vldo_diff; for(i=0; i<18; i=i+1) begin vldo_diff_r[i+1] <= vldo_diff_r[i]; end end else begin vldo_diff_r <= vldo_diff_r; end end wire vldo_r0_h; wire vldo_r0_l; reg vldo_r0; always @(posedge clk or negedge rstn)begin if(rstn==1'b0)begin vldo_r0 <= 0; end else if(vldo_r0_h)begin vldo_r0 <= 1; end else if(vldo_r0_l)begin vldo_r0 <= 0; end end assign vldo_r0_l = (dout_p0_r0 == 0 && dout_p0 == 0 && dout_p0_r2 == 0 && dout_p0_r3 == 0 && dout_p0_r4 == 0 && dout_p0_r5 == 0&& dout_p0_r6 == 0); assign vldo_r0_h = vldo_diff_r[18] == 0 && vldo_diff_r[17] == 1 ; assign vldo = vldo_r0; endmodule