Command: vcs -full64 -sverilog +lint=TFIPC-L +v2k -debug_access+all -q -timescale=1ns/1ps \
+nospecify -l compile.log -f files.f
15 modules and 0 UDP read.
make[1]: Entering directory '/home/ICer/thfu/TailCorr/v05/sim/csrc'
../simv up to date
make[1]: Leaving directory '/home/ICer/thfu/TailCorr/v05/sim/csrc'