//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    MeanIntp_8.v
//  Department            :    
//  Author                :    thfu
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  0.1         2024-09-27      thfu            top module of 8 mean interpolation
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//
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//  Parameter
//
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//  Purpose                 :
//                      
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//  Target Device:        
//  Tool versions:        
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//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------
module MeanIntp_8(
		 	clk,
		 	rstn,
		 	en,
		 	din,  //input
			dout_0,//output
			dout_1,
			dout_2,
			dout_3,
			dout_4,
			dout_5,
			dout_6,
			dout_7
);


input rstn;
input clk;
input  en;

input  signed [15:0] din;
output signed [15:0] dout_0;
output signed [15:0] dout_1;
output signed [15:0] dout_2;
output signed [15:0] dout_3;
output signed [15:0] dout_4;
output signed [15:0] dout_5;
output signed [15:0] dout_6;
output signed [15:0] dout_7;

reg  [15:0]  din_r1;

always@(posedge clk or negedge rstn) 
    if(!rstn)
        begin
                 din_r1  <=  'h0;  
        end
    else  if(en)
        begin
                 din_r1  <=  din;
        end
    else
        begin
                 din_r1  <=  din_r1;
        end

wire  [16:0]  sum_0_1;
assign  sum_0_1 = {{1 {din[15]}},din} - {{1 {din_r1[15]}},din_r1};

wire  signed  [16:0]  diff_1_2;//(din-din_r1)/2 
wire  signed  [16:0]  diff_1_4;//(din-din_r1)/4
wire  signed  [16:0]  diff_1_8;//(din-din_r1)/8

assign  diff_1_2 = {{1 {sum_0_1[16]}},sum_0_1[16:1]};
assign  diff_1_4 = {{2 {sum_0_1[16]}},sum_0_1[16:2]};
assign  diff_1_8 = {{3 {sum_0_1[16]}},sum_0_1[16:3]};

reg  signed  [16:0]  dout_r0;
reg  signed  [16:0]  dout_r1;
reg  signed  [16:0]  dout_r2;
reg  signed  [16:0]  dout_r3;
reg  signed  [16:0]  dout_r4;
reg  signed  [16:0]  dout_r5;
reg  signed  [16:0]  dout_r6;
reg  signed  [16:0]  dout_r7;


always@(posedge clk or negedge rstn) 
    if(!rstn)
        begin
                 dout_r0  <=  'h0;
                 dout_r1  <=  'h0;
                 dout_r2  <=  'h0;
                 dout_r3  <=  'h0;
                 dout_r4  <=  'h0;
                 dout_r5  <=  'h0;
                 dout_r6  <=  'h0;
                 dout_r7  <=  'h0;
        end
    else  if(en)
        begin
                 dout_r0  <=  din_r1;
                 dout_r1  <=  din_r1 + diff_1_8;
                 dout_r2  <=  din_r1 + diff_1_4;
                 dout_r3  <=  din_r1 + diff_1_4 + diff_1_8;
                 dout_r4  <=  din_r1 + diff_1_2;
                 dout_r5  <=  din_r1 + diff_1_2 + diff_1_8;
                 dout_r6  <=  din_r1 + diff_1_2 + diff_1_4;
                 dout_r7  <=  din_r1 + diff_1_2 + diff_1_4 + diff_1_8;
        end
    else
        begin
                 dout_r0  <=  dout_r0; 
                 dout_r1  <=  dout_r1;
                 dout_r2  <=  dout_r2;
                 dout_r3  <=  dout_r3;
                 dout_r4  <=  dout_r4;
                 dout_r5  <=  dout_r5;
                 dout_r6  <=  dout_r6;
                 dout_r7  <=  dout_r7;
        end

assign dout_0 = dout_r0[15:0];
assign dout_1 = dout_r1[15:0];
assign dout_2 = dout_r2[15:0];
assign dout_3 = dout_r3[15:0];
assign dout_4 = dout_r4[15:0];
assign dout_5 = dout_r5[15:0];
assign dout_6 = dout_r6[15:0];
assign dout_7 = dout_r7[15:0];

endmodule