`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/03 15:36:03
// Design Name: 
// Module Name: AxiSpi
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module AxiSpi(
    input           clk,
    input           reset,
    input           WR,          // write en
    input           RD,          // read en
    //input [7  : 0]  Wlength,     // д³¤¶È
    //input [7  : 0]  Rlength,     // ¶Á³¤¶È
    input [31 : 0]  WADDR,       // дµØÖ·
    input [31 : 0]  RADDR,       // ¶ÁµØÖ·

   (* KEEP="TRUE"*) input [31 : 0]  DIN,
    input           WVALID,      // дÊý¾ÝµÄvalid
    input           cmd_s,       // Ö¡¸ñʽ¿ØÖÆ×Ö
    input [4  : 0]  chirpID,
    input [31 : 0]  Nlen,
    
   (* KEEP="TRUE"*)  output          WREADY,      // ¿ÉÒÔдÊý
   (* KEEP="TRUE"*) output          RREADY,      // ¿ÉÒÔ¶ÁÊý
    // read data from spi slave, need to send to axi
   (* KEEP="TRUE"*) output          RVALID,      
   (* KEEP="TRUE"*) output [31 : 0] RDATA,   
    
    // interface to spi slave
    input           spi_slave_bit,
    
   (* KEEP="TRUE"*) output          ss,
   (* KEEP="TRUE"*) output          spi_clk,
   (* KEEP="TRUE"*) output          spi_master_bit
    );

// ÎÞÂÛ¶Áд¶¼ÒªÍ¨¹ýдspi slave µÄ·½Ê½£¬Ö»ÊÇдµÄÖ¸Áͬ    
//axi_slave_mem axi_slave_mem_u(    
//        .clk1(sys_clk),     // write clk
//        .reset(!sys_rst_n),
//        .WR(WR1),
//        .RD(1'b0),
//        .ADDR_WR(ADDR_WR),
//        .ADDR_RD(ADDR_RD),
//        .DIN(DIN),
//        .cmd_s(1'b0),
        
//        .DVALID(DVALID1),
//        .DOUT(DOUT1),
//        .ValidRange(ValidRange1)
//    );

//axi_slave_mem axi_slave_mem_u2(     // ¶Á
//    .clk1(sys_clk),     // write clk
// //   .clk2(sys_clk),     // read clk
//    .reset(!sys_rst_n),
//    .WR(WR2),
//    .RD(1'b1),
//    .ADDR_WR(ADDR_WR2),
//    .ADDR_RD(ADDR_WR2),
//    .DIN(DIN2),
//    .cmd_s(1'b0),
    
//    .DVALID(DVALID2),
//    .DOUT(DOUT2),
//    .ValidRange(ValidRange2)
//);

reg WR_c;   // ¶Á»¹ÊÇдµÄÑ¡Ôñ
always@(posedge clk)
begin
    if(reset)
    begin
        WR_c <= 1'b0;
    end
    else if(WR_c == 1'b0)      // д״̬ÏÂÖ±µ½¶ÁÖ¸Áîµ½À´ÔÙ·´×ª
    begin 
        if(RD)
        WR_c <= 1'b1; 
    end
    else                      // ¶Á״̬ÏÂÖ±µ½Ð´Ö¸Áîµ½À´ÔÙ·´×ª
    begin
        if(WR)             
        WR_c <= 1'b0;
    end
end
// ÓÉÓÚWR_cµÄÔ­Òò£¬ËùÓÐÊäÈ붼ҪºóÑÓÒ»¸öclk²ÅÄܺÍWR_c¶ÔÆë
reg WR_r;
reg RD_r;
reg [31 : 0] WADDR_r;
reg [31 : 0] RADDR_r;
reg [31 : 0] DIN_r;
reg          cmd_sr;
always@(posedge clk)
begin
    if(reset)
    begin
        WADDR_r    <= 32'b0;
        RADDR_r    <= 32'b0;
        DIN_r      <= 32'b0;
        cmd_sr     <= 1'b0; 
        WR_r       <= 1'b0; 
        RD_r       <= 1'b0;      
    end
    else 
    begin 
        WADDR_r    <= WADDR;
        RADDR_r    <= RADDR;
        DIN_r      <= DIN    ;
        cmd_sr     <= cmd_s;  
        WR_r       <= WR;  
        RD_r       <= RD;   
    end
end
wire DVALID;
wire [7 : 0] DOUT;
wire ValidRange;
wire [31 : 0] data_spi_32;
wire WR_mem;
assign WR_mem = WR_r || RD_r;  // ÎÞÂÛ¶Á»¹ÊÇд£¬¶¼ÐèÒª¶Áд
axi_slave_mem axi_slave_mem_u(       // µØÖ·Ö»»á¸øÊ×µØÖ·£¬ºóÃæÐèÒª×Ô¼º²¹ÉÏ£¬»òÕßÏÈ°´Ã¿´ÎÖ»·¢Ò»Ö¡Ð´
        .clk1(clk),     // write clk
        .reset(reset),
        .WR(WR_mem), //WR_r
        .RD(WR_c),
        .ADDR_WR(WADDR_r),
        .ADDR_RD(RADDR_r),
        .DIN(DIN_r),
        .cmd_s(cmd_sr),
        .chirpID(chirpID),
        .Nlen(Nlen),
        
        .DVALID(DVALID),
        .DOUT(DOUT),
        .ValidRange(ValidRange),
        .data_spi_32(data_spi_32)
    );

wire [7 : 0] spi_master_byte;
wire spi_master_valid;
//wire miso; 
spi_master spi_master_u(
    // control signal
    .clk(clk),
    .reset(reset),
    
    //// TX(MOSI) signal
    .Rx_ready(~ValidRange),    // ÐèÒª¶ÁдspiʱÖÃ1
    .axi_byte(DOUT),
    .axi_valid(DVALID),
    
    .ss(ss),      // ƬѡÐźÅ
    .spi_master_bit(spi_master_bit),
    .spi_clk(spi_clk),
    
    // RX(MISO) signal
    .spi_slave_bit(spi_slave_bit),
    .spi_master_byte(spi_master_byte),
    .spi_master_valid(spi_master_valid)
    
    // SPI Interface   
    
    ); 

spi_master_mem spi_master_mem_u(    // ¼ÓÒ»¸öreadyÐźţ¬±íʾ¿ÉÒÔ¶Áд£¨spi´«Êýʱ²»ÄܶÁд£©
        .clk(clk),     
        .reset(reset),
        .RD(WR_c),         // axi
        .ADDR_RD(RADDR_r),    // axi
        .DIN(spi_master_byte),        // spi
        .DVALID(spi_master_valid),     // spi
        .cmd_s(cmd_s),
        .chirpID(chirpID),
        .Nlen(Nlen),
        .data_spi_32(data_spi_32),
        
        .DREADY(~ss),
        
        .DOUT(RDATA),
        .DVALID_o(RVALID)
    ); 

reg ss_r1;
reg ss_r2;
always@(negedge clk)
begin
    if(reset)
    begin
        ss_r1       <= 1'b0; 
	ss_r2       <= 1'b0;     
    end
    else 
    begin 
        ss_r1       <= ss;  
 	ss_r2       <= ss_r1; 
    end
end

assign WREADY = ss_r2 && ss_r1 && ss;
assign RREADY = ~(ss_r2 && ss_r1 && ss);

endmodule