//  Relese History
//  Version     Date            Author          Description
//  0.2         2024-06-14        ZYZ
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :   receive data from spi_master,sent data to PC
// 			  				set reset to output Rdata_PC
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR--------------------------------------------------------------------------------------------------------

module rx_sram(
    input 			clk,
    input 			rstn,

  (* mark_debug="true" *)	  input 	[31:0]		    din         ,
  (* mark_debug="true" *)	  input 			    din_vld     ,
  (* mark_debug="true" *)	  input 			    data_rden_rx,
  (* mark_debug="true" *)	  output	[31:0] 	            Rdata_PC
);

parameter width = 32	;
parameter depth = 65536  ;

//=================================================
function integer clog2(input integer depth);
begin
        for(clog2=0;depth>0;clog2=clog2+1)
                depth =depth>>1;
end
endfunction
//=================================================

localparam aw    = clog2(depth-1);

//=================================================
//wr&rd address
(* mark_debug="true" *)	 reg [aw-1:0]	cnta 	;
(* mark_debug="true" *)	 reg [aw-1:0]	cntb 	;

(* mark_debug="true" *)	 reg 			ena	;
(* mark_debug="true" *)	 reg 			enb	;
(* mark_debug="true" *)	 wire [31:0]	doutb	;

(* mark_debug="true" *)  reg    [31:0]  din_reg;
always @(posedge clk or negedge rstn)
	begin
		if(!rstn ) begin
			din_reg <= 	 1'b0;
		end 
		else begin
			din_reg <=     din;
		end
	end	

(* mark_debug="true" *)  reg data_rden_rx_reg;
always @(posedge clk or negedge rstn)
	begin
		if(!rstn) begin
			data_rden_rx_reg <=         1'b0 ;
		end 
		else begin
		        data_rden_rx_reg <=         data_rden_rx ;
	         end
end

//addra addrb
always @(posedge clk or negedge rstn)
	begin
		if(!rstn) begin
			cnta <=         'h0 ;
		end 
		else if(ena) begin
			cnta <= cnta +  'b1;
		end
		else 
			cnta <= cnta ;
	end

always @(posedge clk or negedge rstn)
	begin
		if(!rstn ) begin
			cntb <= 		'h0;
		end 
		else if(enb) begin
			cntb <= cntb +  'b1;
		end
		else begin
			cntb <= cntb;
		end
	end
		
//enable
always @(posedge clk or negedge rstn)
	begin
		if(!rstn ) begin
			ena <= 	       1'b0;
		end 
		else begin
			ena <=         din_vld;
		end
	end	
always @(posedge clk or negedge rstn)
	begin
		if(!rstn) begin
			enb <=         1'b0 ;
		end 
		else if(data_rden_rx_reg & (cntb <= cnta - 1'b1))begin
		    enb <=         1'b1 ;
	   end
	   else begin
	        enb <=         1'b0 ;
	   end
	end		


reg [31:0] Rdata_PC_reg;
always @(posedge clk or negedge rstn)
	begin
		if(!rstn ) begin
			Rdata_PC_reg <= 	       32'b0;
		end
		else begin
		    Rdata_PC_reg <=            doutb;
		end
	end	
assign Rdata_PC = Rdata_PC_reg;
/*
blk_mem_gen_0 blk_mem_gen_0_inst(
	.clka(clk),
	.ena(1'b1),
	.wea(ena),
	.dina(Rdata_reg),
	.addra(cnta),
	
	.clkb(clk),
	.enb(enb),
	.doutb(doutb),
	.addrb(cntb)
);
*/

spram_model #(
	.width(width),
	.depth(depth)
)spram_inst(
	.clka(clk),
	.ena(~ena),
	.dina(din_reg),
	.addra(cnta),
	
	.clkb(clk),
	.enb(~enb),
	.doutb(doutb),
	.addrb(cntb)
);

endmodule